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Study Of The Calibration Techniques For High Speed And High Resolution Current Steering DACs

Posted on:2018-03-27Degree:DoctorType:Dissertation
Country:ChinaCandidate:K J WuFull Text:PDF
GTID:1318330542477577Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
As a bridge connecting digital domain to analog domain,digital-to-analog converter(DAC)is one of the core modules that limits the performance of the whole system and plays an increasingly important role in applications such as wireless communications,signal synthesis and radar system.The current steering DAC is widely used for high-speed,high-precision DAC design because its signal bandwidth is only affected by the resistance and capacitance of the output node.However,the current-steering DAC intrinsically has many non-ideal factors that greatly limit the performance of DAC.In particular,as DAC applications require toward higher accuracy,higher sampling rates,and higher signal bandwidth,it is very difficult to achieve the high-speed and high-precision requirements due to these non-ideal factors that produce different error sources.Under this background,this paper mainly studies the error sources and its influence in the high speed and high resolution current steering DAC.Corresponding calibration methods are proposed for static error and dynamic error,respectively.The calibration technologies are processed and verified.In the aspect of static mismatch error calibration,this paper analyzes the different mismatch sources of the static error comprehensively which are modeled and deeply theoretical derivation.The window prediction digital foreground self-correction technique is proposed to eliminate the static mismatch error of the current source and increase the performance of DAC.Based on the traditional digital foreground self-tuning technique,the window prediction technique of the value of the mismatch current is introduced,which determines whether the value of the mismatch current is in the given range before the mismatch current is quantized into the corresponding digital code.If the value of the mismatch current is in the window range,the quantization of the mismatch current start from the given range,otherwise from the beginning.Through the introduction of window prediction technology,DAC has small chip area,good linearity,less calibration cycles and power consumption compared with other calibretion mathods.A 12bit 200MS/s current-steering DAC is implemented under40nm CMOS process.Due to the calibration technology,the variation range of the unit current source increases from 0.8%to 2.4%,which will reduce the area of the current source array by 88.88%.In the end,the core area of the DAC is only 0.42mm~2.The errors caused by the reduced current source area are calibrated by the digital foreground self-calibration technology.The experiment test results show that the dynamic performance,SFDR,is 78.8dBc at a low signal frequency and is over 62d Bc for signal frequencies up to the Nyquist rate.The DNL and INL are less thaną0.6LSB andą1.31LSB,respectively.In addition,due to the window prediction technology,the number of calibration cycles decreased by 12.8%during calibration.In the aspect of dynamic mismatch error calibration,The amplitude error and timing error of the current rudder DAC are modeled and analyzed theoretically in this paper.The calibration technique for dynamic error based on the SDR technology is proposed.Firstly,each MSB current source split into two sub-MSB current sources that have the same value of current ideally.Secondly,dynaminc mismatch sensor quantifies the dynaminc mismatch of all sub-MSB current sources and sorts them.Then,all the sub-MSB current sources are regrouped by the principle of minimum residual error to form a new switching sequence of MSB current sources.Due to the SDR technology,the variation range of the unit current source increases from 0.2%to 0.88%,which will reduce the area of the current source array by 93.75%at the same performance.A 14-bit200MS/s current-steering DAC was designed under 40nm CMOS process,the core area of the DAC is 2.21mm~2.The post simulation results show that INL and DNL of the DAC are less than 0.427LSB and 0.23LSB respectively.At 200MS/s,the SFDR is95.51dBc for sinusoidal signals of 17.1875MHz and is over 62dBc for signal frequencies up to the Nyquist rate.
Keywords/Search Tags:current-steering DAC, static error, dynamic error, the window prediction technique, digital calibration
PDF Full Text Request
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