A Study Of 14-Bit High Speed High Precision CMOS D/A Converter

With the rapid development of the field of wireless communication, digital analog converter and analog to digital converter are more important to connect analog signals and digital signals. Due to the rapid promotion of digital circuit processing speed, the development of high performance DAC and ADC has become an important factor restricting the development of the communication chip industry. At the same time, along with the now shrinking process size, difficulty in designing analog chips are continuously improving, which gives high performance DAC designers have brought great challenges. The current steering DAC, which has been used to support the high sampling rate and excellent compatibility with the standard process, has always been the main structure of the super high speed DAC designers. But there are also many problems in the current steering DAC. The energy of the switch signals and the static and dynamic mismatch in the current source array can greatly limit the linearity of DAC. In this paper, the above effects are optimized and improved to improve the linearity of DAC.In this paper, the design of the standard CMOS production process based on the SMIC0.18 ?m, designed a sampling rate of 14 bit high speed and high precision current steering DAC 3GSPS. The DAC uses a 4 most significant bits with innovative grouping random rotation binary code, and 10 low significant bits with conventional binary code. The method can be used to find a balance point between the complexity of the circuit and the dynamic matching performance of the circuit, Then the four channel data interpolation technique is used to achieve the high frequency signal of and the high frequency signal of DAC is achieved to improve the performance of 3GSPS, In this paper, the structure of the unit current source is used to improve the output impedance of current source, and the four phase switch is used to reduce the influence of the control signal to the DAC linearity and improve the overall performance of DAC.The simulation of the basic function of the whole circuit and the simulation of the(SFDR), the simulation results show that the sampling frequency reaches 3GHz, and the SFDR reaches 75 d B. In the stage of the layout of the layout, the layout of the Virtuoso graphic layout design tool is used in the Cadence environment, In strict accordance with the requirements of the SMIC process and the design method of analog layout design, and in the process of the design of the impact of the use of current source array matching technology to optimize the layout of the current source array.