High Speed And High Accuracy Current-Steering Digitial-to-Analog Converter Resuich And Disign

Nowadays wireless communication system exploiting wideband and multicarrier modulation,such as 802.11 ac,and 4G-LTE,in these application,need much lower signal distortion and noise to improve the signal transmission quality.While DAC plays a quiet important role in a transmitter,DAC makes a bridge between baseband digital signal and RF front-end,so the performance of DAC decides the best performance which transmitter can achieve.Also in those application,the SFDR,IM3 and NSD of DAC are important.Current-steering is an inherent high speed architecture,for the typical 50? static resistance load.But the nonlinearity of current-steering DAC is the main problem caused by mismatch,doping,temperature,and layout,e.g.Low speed DAC mainly cares about static error,and uses calibration or DEM which achieves a good SFDR.But when the sample rate increases to GHz,dynamic error becomes the main problem effect the system linearity,which will increase NSD a lot by using DEM only.Also the static calibration cannot calibrate dynamic error,so the SFDR will get much worse when the frequency increases.In this work,a segmented 6b MSB DEM and 8b LSB binary 1G 14 bit current steering DAC circuits design is introduced.Based on the dynamic error and parasitic error found in circuits design,a new totally sort-and-combine and mixed DEM method is presented.With T3D-SC,the static error and dynamic error of not only MSB cells,but also LSB group can be calibrated in only once calibration.With DEM in middle bits,middle bits signal dependence nonlinearity decreases.