16-BIT Current Steering DAC DMM Calibration Algorithm Modeling And Digital Implementation

As the bridge connecting the digital world and the analog world,digital-to-analog converters have always been the focus of research in the IC industry at home and abroad.This paper studies the non-ideal factors of 16-bit current steering DAC based on 40 nm CMOS,and based on matlab software modeling the impact of non-ideal factors on DAC and determining the segmentation mode of DAC.Then a new method based on DMM algorithm is proposed.Correct the algorithm and verify it with matlab modeling.The calibration circuit implementation of this design is accomplished by combining the digital back end of the integrated circuit under deep sub-micron,and the basic flow of DRC,LVS,and voltage drop verification is finally performed on the layout.This article first studied the working principle of the DAC and the dynamic and static performance indicators to measure the DAC performance.Then listed several existing structures of the DAC and analyzed their respective advantages and disadvantages,and confirmed the design of the segmented current steering DAC structure.Thenaccording to the matlab software,confirm the 5+5+6 segmentation method of this design.Then,the main non-ideal factors influencing the performance of the current steering DAC and its influence on the DAC performance are studied in depth.According to the matlab software,a non-ideal factor model of the current rudder DAC is used to verify the non-ideal factors of the DAC.Then,based on the DMM correction algorithm,an improved way to add redundant current sources is proposed.A reasonable behavioral level model is established through the matlab tool,and the number of redundant current sources is determined to be 20.Based on the 40 nm CMOS process,using DC,ICC,PR and other related integrated circuit back-end EDA software,after a series of back-end processes,the DAC Calibration circuit design.Finally,the post-imitation verification is performed after the digital circuit layout generated by the back-end is stitched with the analog circuit board.The power consumption of the current steering DAC of this design is 120 m W,and the area of the DAC core layout is 4mm2,the area of the digital circuit is 0.5mm2.The verification results show that the DNL of the DAC is 0.233 LSB and the INL is 0.377 LSB.When the frequency of the input signal is 17.1875 MHz,the SFDR of the DAC is 91.77 d B.When the input signal is 92.1875 MHz,the SFDR is 87.26 dB.