Research On Hardened Latch Designs For Anti-Single Event Upset In Integrated Circuits

Due to semiconductor technology scaling,integrated circuits have been widely used in various fields,making them an indispensable part of society.With the arrival of the post-Moore era,the integration of electronic chips has increased again,making its process size into the nanometer scale,and this results in smaller device capacitance.At the same time,the improvement of circuit integration leads to the reduction of the distance between semiconductor devices,which makes the influence of radiation effect on circuit reliability more and more serious.Among them,the single-particle effect is one of the radiation effects,and the reliability of the circuit has a certain effect.And soft errors caused by single-event effects affect the reliability of integrated circuits,and it is indispensable to protect them.Although the miniaturization of the circuit has brought performance and area optimization,making the integrated circuit more sensitive to soft errors,and causing the original protective design has become less reliable.As a storage element in the circuit,it is of great significance to reinforce the latch against radiation.Aiming at the latch in the radiation environment is prone to soft errors,resulting in a single event upset.At the same time,some latches have a high cost and low reliability.Based on clock-gating(CG)technology and high-speed transmission path technology,this thesis proposes a high-performance triple node upset(TNU)tolerant(HTNUTR)latch.A highly robust TNU self-recoverable(HTNURE)latch is proposed to improve the reliability further.The main contents are as follows:1.HTNUTR latch:Based on the traditional DICE,a new connection mode of dual-mode interlock is used.Adding transistors like a switch in the DICE cells,and its gate of the transistor is driven by other DICE cells,can ensure its selfrecovery for double node upsets(DNUs).By using CG-based C elements in the output,it can tolerate the TNU to improve its reliability.Simulation results demonstrate that the latch can tolerate TNU.Compared with the introduced TNUtolerant latches,the HTNUTR latch reduces the number of transistors,transmission delay,power dissipation,and power delay product(PDP)by 34.1%,58.7%,21.7%,and 68.3%,respectively.2.HTNURE Latch:Based on the traditional C elements,a storage module is constituted by four sequentially connected C elements.The triple module redundancy is used to interlock with three storage modules to satisfy the highreliability purpose so that it has the capability of TNU self-recovery.And there are two CG-based C elements in each module,which are used to cut off current competition in transparent mode and reduce the power dissipation.Simulation results demonstrate that the latch has the ability of TNU self-recovery.Compared with the introduced TNU self-recoverable latches,the HTNURE latch reduces the number of transistors,transmission delay,power dissipation,and PDP by 29.02%,30.25%,76.34%,and 84.01%,respectively.Figure [37] Table [9] Reference [76]...