A10-bit100MSPS CMOS Folding And Interpolating A/D Converter

The research and development of analog to digital converter IP with high speed,low power and small area is of great significance in the field of SOC. With theexcellent features in speed, power consumption and area, folding and interpolatinganalog to digital converter becomes a study hotspot in recent years.The research employs the folding and interpolating structure to design a highspeed analog to digital converter with1.8V power supply,10bit resolution and100MS/s sampling rate by the use of standard CMOS process. Because of thefrequency-multiplier effect and the large input offset voltage, it is needed to carry ontradeoff between folding coefficient and interpolating coefficient carefully. Theresearch employs3*3pipelined folding structure to achieve9folding coefficient, andemploys*2and*4interpolating in the folding process. Besides, the research employspipelining technique and interpolating error modification technique to overcome thefrequency-multiplier effect. With the use of pipelining technique, the demand ofcomparators and folders is relaxed, and the techniques of offset cancellation anddistributed T/H can be used.The research adopts SMIC0.18μm1P6M process to accomplish the circuit andlayout design. The effective area of the chip is1.6mm*1.6mm. At the situation of1.8Vpower supply voltage,100MS/s sampling rate and50MHz sine wave input, the SNDRis56.79dB, SFDR68.21, and ENOB9.1. The whole power consumption is120mW.