Ultra-high-speed Adc Folding And Interpolating Structure And Circuit Design

The fast development of digital processing technology requires analog-digital converter (ADC) with higher speed.In order to satisfy this requirement, ADC have been made a rapid progess towards ultra high speed. There are two typical architectures for ultra high speed ADC, one is flash ADC, the other is folding and interpolating ADC. Folding and Interpolating structure with less the number of comparators, less area, and lower power consumption become the first choice for ultra high-speed ADC.This thesis studies the structures and designs the circuits for 8-bit 400MSPS folding and interpolation ADC.This paper presents a general introduction on the folding and interpolating ADC firstly, including its principle and circuits.Comparison of the advantages and disadvantages of folding circuits and interpolation circuits, folding circuit and interpolation circuit is determined. Base on the trade-off between speed, power dissipation and accuracy, the folding and interpolating ADC system are analyzed, and the relationship between the folding rate,interpolation rate,and the number of folding blocks are discussed.Analysis of the non-idealities in folding and interpolation ADC and two level cascade folding circuit are discussed.Base on nonlinearity analysis of the preamplifier in folding and interpolation ADC,a novel differential difference preamplifier was designed to reduce the nonlinearity of the traditional preamplifier. In order to reduce the frequency multiplying effect of folding circuit,distributed sample and hold circuits are designed. By applying the distributed sample and hold circuits, the requirements of bandwidth of folding circuit are reduced. An analysis of the relationship between the resistor offset averaging network and capacitance offset averaging network and the differential nonlinearity(DNL) and the integral nonlinearity(INL) is presented. To improve the DNL and INL of the ADC, the resistor offset averaging network and capacitance offset averaging network are designed. A novel folding circuit is designed to reduce the affect caused by the mismatch of currents, whose folding rate is three. Finally, taking into account the circuit threshold voltage mismatch and channel length modulation effect on the interpolation accuracy,a current mirror-based interpolator whose interpolation rate is eight is designed.The circuit is simulated with the simulation tool of Cadence.The simulaton results show that the gain of folding circuit is 8.165dB with a unity-gain bandwidth of 1.259GHz,and the maximum zero-crossing error is 0.03mV,much smaller than 1LSB of the circuit. The maximum zero-crossing error of folding and interpolation circuit is 1.45mV,smaller than 1LSB of the circuit.,satisfy the design requirements of the 8-bit 400MSPS folding and interpolation ADC.In the end ,considering the devices matching and the circuit symmetry ,the layout of folding and interpolation circuits are drewed and the total area is 600μm×237μm。...