The Research And Circuit Implementation Of Foreground Calibration Technique In Folding & Interpolating A/D Converter

By using folding and interpolation technique, the folding and interpolating A/D converter has a good potential in the field of ultrahigh speed and high precision A/D converter. However, due to the adoption of the full open loop structure, the offset error caused by the mismatch of the process mismatch will severely limit the sampling speed.Domestic and foreign researchers have proposed and adopted a variety of calibration techniques to eliminate, the effects of offset error on the performance of the folding and interpolating A/D converter. Among them, the foreground calibration technology is simple and efficient, and design complexity is small, which has important research significance and application value in improving the performance of the folding and interpolating A/D converter. This will be the core issue of this thesis.Firstly, this thesis introduces the working principle of folding and interpolating A/D converter,and two channel time interleaved six level pipeline cascade architecture is adopted according to the design indexes of 1 Obits, 1GSps, then the non-ideal factors such as offset error and gain error inside a channel and among channels are deeply analyzed and modeled. Secondly, this thesis studies the foreground calibration technology using current steering DAC and designs the calibration process and error compensation control system to calibrate the preamplifier output offset, the second folder and the third folder input offset and tail current source mismatch and ensure the accurate reference voltage range. Finally, this thesis designs foreground calibration circuit of the folding and interpolating A/D converter, including the foreground calibration vector DAC circuit for generating calibration reference voltage signals, and the current steering DAC circuit for compensating preamplifier output offset. The current steering DAC circuit uses the "5+2" segmented structure, namely the high 5 bits use thermometer code to control unit current sources, and the low 2 bits use binary to control weighted current sources. This structure ensures the accuracy and reduces the circuit area consumption. In addition, the bandgap reference voltage source circuit and the current bias circuit are designed.In this thesis, circuit design and simulation based on TSMC 0.18?m CMOS technology and Cadence Spectre software are presented. The simulation results show that the designed error compensation control system can make the output signals after the calibration continuously approach reference voltage signals and realize the error calibration, then the offset error of the folding and interpolating A/D converter is eliminated effectively. The resolution of foreground calibration vector DAC circuit can achieve 7.92bits, and the number of the calibration reference voltage signals produced by the DAC circuit can meet the requirement of the number of the zero crossing which is needed to be calibrated in the first three stages. The zero-crossing compensationcaused by single step of the corresponding current steering DAC calibration circuit is 0.544mV, and meets the precision of compensation required by the precision index of A/D converter,and the whole compensation range is 70.169mV,and larger than the maximum offset error in the analog quantization path .The temperature coefficient of the designed bandgap reference voltage circuit is 14.01ppm/·C and the PSRR is 78.66dB.