Design Of High-speed CMOS Charge Pump Phase-locked Loop

With the rapid development of integrated circuit design and CMOS process, IC design has entered SoC phase. Phase Locked Loop (PLL) as a clock source,can be widely used in SoC system, it is an important part of modern wireless communication,its function determines the property of the system. This paper focuses on the design and implementation of high-speed Charge-Pump Phase Locked Loop (CPPLL), to study its theory, mathematical model, circuit design and simulation, production test.Based on TSMC 0.18 ?m 1P6M mixed signal CMOS process, a CPPLL with quick lock time, wide output frequency range and low phase noise has been designed. Using"Top to Down" method,complete the circuit from system level to CMOS level.Analysis the non-ideal effect such as dead zone, current mismatch,stability,and start-up problem. Optimize the circuit and eliminate its non-ideal effect. Using Cadence Spectre to simulate the circuit. The circuit has a tuning range of 1.9 GHz to 2.6 GHz with reference signal from 23 MHz to 600 HMz. At central frequency 2.3 GHz, the phase noise of the VCO is -112.9 dBc/Hz at 10 MHz frequency offset.Execute layout design, separate digital modules and analog modules, using special method to lower phase noise. After the layout verification, the circuit was taped out and tested. The results show that the circuit satisfies the function requirement and can work on the rails.This CPPLL circuit can used in clock synchronization circuit, frequency synthesizer,clock recovery circuit, multi-phase sampling circuit, etc.