The Design And Implementation Of Charge Pump Phase-Locked Loop Based On 0.18μm CMOS Process

Based on SMIC 0.18μm standard CMOS process, a charge pump phase-locked loop with wide output frequency range, low phase noise and can be integrated in SOC system has been designed. The PLL is focused on clock frequency multiplying from the reference frequency range 10MHz~50MHz to output frequency range 260MHz~400MHz, which meets the requirement of clock signal in most high speed integrated circuits.The whole design was carried out using the Top-Down method, flowing through from system level to circuit level, and to the chip level. Firstly, the system level model was established using VerilogA high-grade language and Matlab tool, and the system loop parameters were optimized on the basis of mathematic model analyzing and behavior-level simulating results; According to the specification and guideline brought forward foregoing, the PLL transistor-level circuit was designed and simulated in detail. Aiming to eliminating the non-ideal effect such as dead zone, current mismatching and charge-sharing in circuit, special consideration was taken into account under the guidance of analog circuit design and phase locking theory. After the layout design and verification, the design was taped out and tested. The results show that the chip satisfies the function reqirement and can work on the rails.In the end, further research was conducted. The improvement in respect to output frequency range and noise characteristic was accomplished by means of ring VCO delay cell reconfiguration and loop bandwidth optimization. The output frequency range achieves 797.1MHz~1.272GHz while the phase noise reduced to less than -100dB/Hz.The content of the dissertation can be used as guidance to the design of phase locked loop as well as other non-linear systems, also the method and the achievement are of significant value both in theory and application.