The Study And Design Of CMOS High-speed Phase Locked Loop

Phase locked loop(PLL)frequency synthesizerihas been widely implemented in communication and microprocessor System, and it has became the required module in the VLSI along with the development of IC and SOC technology. Especially in the realm of wireless communication and high speed processor, the higher requirements for PLL circuit performance is proposed. Therefore, the PLL circuit performance on the high-speed condition is challenged currently.The thesis is base on the research for the pLL technology development history and current state, analyzing the mathematics model from the perspective of PLL system working principle. Besides, the thesis also does the further research for tracing and capturing its performance, and also deducting each parameter of closed circuit with details. Finally, it obtains the conclusion of PLL mathematics theory analysis.The project PLL design is for adapting high-frequency electricity environment. The circuit introduces the current leading structure- mathematics and models combined Charge-pump PLL。Meanwhile, the circuit design is based on the 0.35um COMS technology, simulating for each module and the entire system of Charge-pump PLL by Hspice. The simulation result shows that with the 3.3v voltage, inputting 250mhz referenced signal, the output signal central frequency is 500mhz , and.utilizing 2 channels division for divisional frequency circuit, the capture time is lus, which achieves the design requirement.