FT-SerDes Receiver Design

SerDes is a time division multiplexing(TDM), peer(P2P) serial communications technology, namely the sending end, multi-channel low-speed parallel signal is converted into high-speed serial signals, via the transmission media(optical or copper)Finally, at the receiving end, high-speed serial signal is converted into low-speed parallel signals again. This point to point serial communication technology can make full use of the channel capacity of the transmission media, reducing the required number of transmission channels and the device pin count, thereby greatly reducing communication costs.Author involved in a FT-SerDes(hereinafter referred to as SerDes) research task and assume its receiver design the SerDes based on 40 nm standard CMOS process, the maximum transmission rate 5Gbps. This paper introduces each SerDes receiver units and it works to complete the design verification and layout SerDes receiver circuit,which receives support 1.25, 2.5, 3.125 and 5 Gbps data rate, to achieve compensation for the data signal amplification sampling and serial to parallel conversion functions.Receiver Design for each unit design, the main work is as follows:1.The impedance matching circuit design dichotomy algorithm, can quickly achieve impedance matching, reduced reflection, to ensure signal quality;2.Equalizer with multi-stage cascade amplifier feedback loop combination of methods to compensate for high frequency attenuation achieved signal 15 dB fixed gain amplifier;3.Sampling circuit to achieve high-speed latched comparator, can quickly extract data information, and the sampling of the comparator can operate at higher transfer rates(about 20Gbps), for higher-speed Serdes interfaces sampler research is a good reference value;4.Serial to parallel conversion circuit uses the traditional tree deserializer structure,structure classic, can better solve the timing issues;5.Designed Comma detection unit(boundary detection unit), use Comma signal indicating byte border, to verify the alignment of data;6.Design differential signal strength detection unit, real-time monitoring of data for determining whether the receiver work, save power.7.Of the territory and the overall layout of each unit customization and simulation,verification of the correctness of the design.During simulation using Verilog-A simulation of noise source, simulate the SerDes receiver systems various noise sources inherent in the use of tools for Hspice simulation results show that the receiver is working properly, the performance indicators to meet project requirements.