Design Of An Adaptive Equalizer At The Receiver Of 12.5Gb/s SerDes System

With the continuous improvement of communication speed requirements,SerDes has gradually become a popular technology for high-speed interfaces due to its low cost,strong anti-interference,and high transmission rate.However,the inter-symbol interference caused by the non-ideal characteristics of the channel limits the increase in the rate of the SerDes system,and the use of equalization techniques to compensate for signal distortion becomes a necessary step.Therefore,the research of equalization technology in SerDes system has important application value.An adaptive equalizer for the receiving end of the 12.5Gb/s SerDes system is designed in this article.Starting from the frequency domain loss characteristics of the channel,for its high-frequency attenuation characteristics,a continuous-time linear equalizer is used as the main equalization circuit to compensate for the channel loss.At the same time,a negative capacitance circuit is added to expand the bandwidth and increase the gain.At the same time,an adaptive method of spectrum energy detection is used to generate an adaptive control voltage,and the equalizer can be controlled to adaptively change with the changes of the channel,environment,and system.The equalization circuit part is composed of a three-stage CTLE cascade.The high-frequency compensation capability at the target frequency is 17 d B?20d B.The high-frequency compensation principle is based on the source degradation characteristics of the amplifier,and the dynamic range depends on the source degradation capacitance.This capacitor is a MOS capacitor,and its capacitance is controlled by an adaptive control voltage.In order to allow the equalizer to adapt to changes in the application environment,an adaptive method of spectrum energy detection is adopted,by detecting the difference between the high and low frequency energy of the signal,and feeding it back to the equalization circuit as a control signal.In order to reduce the difference in system output eye diagrams at different temperatures,a temperature compensation circuit is designed in this article.The zero temperature coefficient current and the positive temperature coefficient current are used to generate a negative temperature coefficient voltage,which is used as a control signal to control another set of source degeneration capacitors in the CTLE to correct the deviation caused by the temperature to the system.The circuit and layout are designed based on TSMC CMOS 40 nm process,and simulation verification is performed.A 17-inch Nelco4000-6 backplane channel model was added to the simulation,and the channel has 18 d B attenuation at the Nyquist bandwidth(6.25G).The post-simulation results show that under a typical process angle,the eye openings at-5?,40?,and 85? are all above 0.76UI.