Design Of Adaptive Equalizer And VCO In High-speed SERDES

With the rapid growth of modern society information, great progress and improve the performance of integrated circuits and multimedia technologies, the amount of communication data transmission must have corresponding to the speed increase, and therefore the demand for communications bandwidth and signal rate also increases day by day, in this context, SerDes is becoming one of the most commonly used data transmission system configuration.The adaptive decision feedback equalizer designed in this paper is applied to the receiver. It is located in the feed-forward equalizer to eliminate inter-symbol interference after the standard components, firstly based on TSMC 65nm CMOS technology, this paper focuses on the design and implementation of the adaptive decision feedback, which has the equalization module, error detection module and a coefficient updating module of three modules, the adaptive decision feedback uses equalization module to achieve balanced results, using the error detection module and a coefficient update module adaptive function, at the same time in order to achieve higher work rate, decision feedback equalization circuit uses a half-rate structure. After the simulation results show that the adaptive decision feedback equalizer initially meet the design requirements at input data rate of 20Gb/s and the system clock of 10GHz.This paper then design a VCO used in CDR, discusses in detail the basic principles of LC VCO, a careful analysis of the VCO phase noise model, and phase noise optimization measures proposed, the final design low phase noise LC voltage-controlled oscillator. After the simulation results show that the phase noise is -104.1dBc/Hz@1MHz to meet the design specifications with a 1V power supply and the work rate of 20GHz.