Research And Chip Design Of High Speed Adaptive Continuous Time Linear Equalizer

With the further development of electronic communication systems,the demand of data transmission rates is increasingly demanding data transmission rates.Since parallel transmission does not meet the requirements of increasing data transmission rates,Serdes technology has gradually become the primary choice for people.However,there is a non-ideal factor such as dielectric loss,skin effect,such as a wired transmission channel,which causes the distortion of the signal,and severely reduces the signal quality of the receiving end.In order to restore the signal quality of the receiving end,the balanced technology has become an essential part of the high-speed Serdes system.The high-speed adaptive equalizer studied in this paper is important for the transmission of high-speed serial communication systems.This paper is designed with an adaptive continuous time linear equalizer for 10Gbps,which consists of a continuous time linear equalizer module,an output buffer module,and an adaptive module.Where channel attenuation uses the S parameters of the FR-4 PCB sheet of ADS simulation.In the continuous time linear equalizer(CTLE),in order to expand bandwidth,an inductive peak,active negative feedback,and source degradation,wherein the inductive pendant is an active inductive structure,and the equalizer is realized while reducing the area.High frequency adjustable.The equalizer uses two-stage equilibrium unit-level way to increase gain,and the first stage uses a dual input structure to improve the gain adjustable range.The adaptive module uses spectrum balancing technology to compare high-frequency and low frequency average power,generate a voltage to control equalizer equilibrium capabilities to achieve the effect of adjusting the gain size.The output buffer module uses the three-stage amplifier cascading structure,using the FT multiplier structure to reduce the input capacitance,and use the induction peak and the bandwidth of the buffer such as source negative feedback.Finally,the layout of the overall circuit is completed by a 0.18?m CMOS process.After the link of the link,the channel is at a 50 cm long analog channel at the signal rate of10 Gbps,and the channel is attenuated to-14.24d B,and the transmission chain The output of the road is 250m V_diffp-p,and the output jitter is 0.35UI.The entire chip is 760×365?m²,and The power consumption of equalizer circuit is 11.89mW.