Font Size: a A A

Modeling Of High Speed Serial System And Design Of Adaptive Analog Equalizer

Posted on:2017-02-11Degree:MasterType:Thesis
Country:ChinaCandidate:X L WangFull Text:PDF
GTID:2308330488457842Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the proposal and popularity of a series of new techniques including Cloud Computing, Big Data and Mobile Internet, it seems that the requirement of data transmission rate is increasing day by day. Due to the traditional parallel transmission is difficult to achieve high speed transmission, serial communication link gradually becomes the mainstream transmission mode. SerDes technology also has been widely used because of high transfer rate, low cast and other advantages. On the other hand, inter symbol interference caused by the nonideal characteristics of the channel is a key factor to affect the advance of data rate. Equalization technology becomes the key part in SerDes system to compensate signal distortion. Therefore, the research of SerDes system and equalization technology has important application value.This paper studies the modeling of high speed serial system. The modeling including the modeling of pre-emphasis and continuous time linear equalizer based on Matlab and the modeling of combined equalization of serial system based on ADS. Through modeling by Matlab, this paper analyses the influence of different parameters on the performance of pre-emphasis and continuous time linear equalizer. The combined equalizer of serial link is analysed through the simulation by ADS platform. By observation and comparison of the performance of different combined equalizer structure, the results show that CTLE+2-tap DFE is the optimum combined equalization architecture with a tradeoff of performance and implementation.This paper also studies the design of adaptive analog equalizer that works at lOGb/s using 0.18μm CMOS process. High-frequency boosting filter is implemented with source degradation and inductive peaking technique. The adaptive is achieved through the comparison of transition time to generate a control signal that feedbacks to equalization filter. The equalizer chip occupies an area of 0.69x0.65=0.45mm2.The post simulation results show that lOGb/s PRBS pass through 18 inch PCB channel has serious inter symbol interference and the eye diagram is basically closed. The eye diagram is improved after adaptive analog equalizer, which indicates that the adaptive analog equalizer can reduce inter symbol interference, improve the signal quality and improve the signal eye.With the trend of the increasing of data rate, the modeling of high speed serial system and design of adaptive analog equalizer have great significance for the design and implement of receiver in serial link.
Keywords/Search Tags:SerDes, equalizer, adaptive, eye diagram
PDF Full Text Request
Related items