Serdes Interface Circuit Design Based On 8b/10b Coding Techniques

SerDes (abbreviation for Serializer/Deserializer) is an interface device for long-distance high-speed communication. As physical layer implementations of communication protocol such as PCI-Express, Gigabit Ethernet and fiber optic communications, SerDes interfaces are widely applied in the high-speed interconnection among chips, boards and equipments.This article introduces theories and applications of four types of SerDes architecture, and establishes the design of 8b/10b SerDes interface circuit through a top-down design methodology in regards to the analysis of the general structure, the function model and the performance parameters of 8b/10b SerDes. In the proposed methodology, the architecture, port features, the functional mode and the technical specifications are primarily defined, technical specifications and implementation techniques of each sub-module are determined following the division of the entire circuit into several sub-modules, and finally the integrated 8b/10b SerDes interface is functionally verified by simulation after the sub-modules are incorporated into an entire circuit.Chapter IV demonstrates the design and verification of digital modules of the 8b/10b SerDes including the 8b/10b encoder/decoder, the Comma detector and the serial to parallel and parallel to serial conversion circuit. Because the 8b/10b encoder/decoder and the comma detector circuit have low working frequencies, they can be designed and verified in an approach of semi-custom design. Based on the rationales for 8b/10b encoding/decoding and comma detection, the situations in which the comma detector may encounter an error have been summarized, and the RTL level circuits of the encoder/decoder and the comma detector have been designed and verified by the functional simulation tool, Modelsim. Outcomes of simulation suggest that the 8b/10b encoder/decoder and the Comma detector function properly and meetthe design requirements. The serial to parallel and parallel to serial conversion circuit is appropriate to design and verify in full custom methodology. Outcomes of simulation by Hspice indicate that the circuit meets the performance requirements.In the last section of the article, the 8b/10b encoder/decoder and the comma detector are constructed using the logic synthesis tool, Design Compiler. The mixed signal simulation platform built on Hsim and NC-Verilog is established to complete functional verification of the whole chip and verification outcomes reveal that four designed functional modes of the SerDes chip, including the power-down mode, the simplex mode, the duplex mode and the test mode work precisely. The power dissipation of the chip working at duplex mode is 330mW, the the bit error rate is lower than 10-12 when the the bit rate is 2.5Gbps.