Design Of2.5Gbps Serdes Transmitter End

With the development of information industry and many kinds of electronic products’emerging, people’s living standard is improving. With the continuously improving ability ofthe computer processor, a huge amount of high-speed data uninterrupted transmission hasbecome the key to support the development of the information industry. With the advent ofserial interface technology, the bottleneck on speed parallel interface has been broken andthe data transmission problems in high-speed data communication industry have beensuccessfully solved. With the improvement of the transmission rate, various serial interfaceshave also appeared, a large number of interface chip based on LVDS, VML, CMLtechnology are producting. But the problems in the serial interface can also seriously affectthe quality of high-speed data transmission. Among them, the high-frequency loss of thechannel has become a key factor limiting the performance of high-speed data transmissionsystems. In addition, other non-ideal factors in circuits are also important factors in thehigh-speed transmission. Therefore, the designers need to understand these issues in depthand make solutions.In this paper, some critical issues in high-speed interconnect systems have beenstudied deeply, and the circuit design of TX part in SERDES system has been completed.Firstly, the characteristics of the interconnect channel is analyzed and the channel model isestablished. Secondly, the signal integrity of high-speed interconnect system is analyszedand detailing presentations and solutions for the non-ideal factors on data transmission linkis given. Then, presenting a brief introduction to some current LVDS, VML, CML andother interface circuits which are widely used in the industry, determine to adopt the CMLtechnology2.5Gbps transmission rate based on the SMIC180nm process.To compensate thehigh-frequency loss of the channel pre-emphasis technique is used in this design. Finally, adetailed analysis of the overall design is proposed in the paper and the layout is completed.In the Cadence platform, each module and the overall circuit are simulated using thesimulator called Spectre and the pre-simulation and post-simulation results are presented.In the last chapter, a summary of this paper is made and some of the issues stillexisting in this design and the solutions are presented.