Design Of A 12.5Gb/s SerDes Transmitter Equalizer

In recent years,with the rapid development of artificial intelligence,cloud computing,big data and other technologies,the demand for data transmission rate is higher and higher.High data transmission capability depends on the support of the underlying hardware system.Traditional parallel transmission is limited by data clock synchronization in high-speed transmission,so serial transmission becomes the main transmission mode in high-speed transmission.SerDes is a kind of mainstream serial transmission technology.With less output interface and strong anti-interference ability,it has become a hot research field in academic and industrial circles at home and abroad.In this thesis,a SerDes transmitter equalizer with transmission rate of 12.5Gb/s is designed.The overall architecture adopts feedforward equalizer structure,which is mainly composed of delay module,adder module and tap coefficient control module.The delay module mainly generates 3 channels of 12.5Gb/s signal with one symbol delay,which is realized by using finite pulse generator and direct 4:1 multiplexer,and adds single to double circuit and pre drive circuit to improve anti-interference ability and signal drive ability.An improved impedance calibration loop is designed to calibrate the impedance of a single drive unit,and the appropriate series resistance and MOS tube size are determined by simulation.When balancing,the influence of the swing and impedance with the V_ds of MOS tube is smaller.Compared with the traditional impedance calibration,the change of V_ds is 2.5 times smaller,and the output swing is only 5.3%.A voltage stabilizing circuit is added,and the differential output swing can be adjusted by adjusting the reference voltage.Finally,four comparators are used to compare the control signal with the reference level.As a result,the driving unit is controlled to adjust the tap coefficient and reduce the number of control signals.The circuit and layout are designed based on TSMC 40nm process.The overall layout area is 0.019 mm².The post simulation results show that the output swing can achieve 0.322V?0.719V,the equalization range is 0 to 9.5d B,the maximum jitter is 0.089UI,and the power consumption under the maximum output swing is 17.10m W.