A 40 Gb/s PAM4 Serdes Receiver In 65nm CMOS Technology

With the increasing communication rate,the impact of channel non-ideality on data transmission is also becoming more serious.In particular,with the introduction of the 400 G Ethernet standard,the rate of a single lane will reach 50 Gb/s,resulting in a channel bandwidth that is difficult to meet the requirements of conventional NRZ signals.The four-level pulse amplitude modulation(PAM4)signals,since each symbol contains two bits of information,the PAM4 signal requires only half the bandwidth of the NRZ signal at the same rate,making it widely used in ultra-fast Serial link communication system.This thesis focus on the design and implementation of high-speed SerDes receiver circuit based on PAM4 signal.Firstly,the IBIS-AMI model of high-speed PAM4 serial communication link is established,and the influence of channel non-ideality on data transmission is analyzed through simulation.On this basis,a 40-Gb/s PAM4 signal receiver was designed using 65 nm CMOS technology,including key modules such as continuous-time linear equalizer(CTLE),3-level slicer,PAM4 decoder,and clock and data recovery circuit(CDR).The CTLE circuit uses capacitance degradation technology to extend the circuit bandwidth.The 3-level slicer special designed for PAM4 signal consists of a voltage shifting-amplifier and a limiting amplifier.The center of the 3 eyes of the PAM4 signal eye can be respectively moved to the 0 level to perform amplitude limiting amplification,and the corresponding thermometer codes are generated.Finally,the PAM4 decoder decodes the thermometer code into two 20Gb/s NRZ signals.This thesis also designed a Bang-Bang type 20Gb/s clock and data recovery circuit(CDR)based on PLL.The entire CDR circuit includes full-rate Bang-Bang phase detector,V/I converter,low-pass filter and voltage-controlled oscillation.(VCO).In order to increase the circuit speed,the latch in the phase detector uses a pseudo-differential structure and uses a high threshold transistor to reduce the load capacitance and reduce the attenuation of the clock signal.At the same time,the XOR gate in the phase detector adopts a completely symmetrical structure,which avoids the problem of signal asymmetry.The Q of the resonant cavity's inductance and capacitance was optimized when designing the VCO.This thesis completes the layout design and post-emulation of the entire receiver circuit.The layout area is(including pad)715?m?520?m.The post-simulation results show that the receiving circuit can restore two parallel NRZ signals correctly from input 40Gb/s PAM4 signals with inter-code interference.the phase noise of the VCO is-108dBc/Hz at 1MHz,the recovered clock jitter is 2.1ps,and the final output of the two 20Gb/s NRZ data's eye opening spread reaches 0.85 UI with jitter of 3.2ps.At 1.2V,the power consumption is 270 mW.