Design Of CDR And FFE In 20Gb/S High-Speed SerDes

SerDes is a mainstream serial communications technology, which is multiplexing multi low speed data channel into single high-speed signal at the transmitting end, then sending it through the transmission medium (fiber or backplane), and finally de-multiplexing into the low speed parallel signals at the receiving end. This technique takes full advantage of the serial communication channel capacity, greatly reducing the cost of communication, and can meet the I/O interface requirements for today’s mass data exchange.In high-speed SerDes chip applications, in order to be able to transmit high-speed data, the clock is often be hidden into the serial data. Thus, clock and data recovery circuits (CDR) must be utilized in the SerDes receiver to receive the high-speed serial data, determine the phase of the signal, extract the clock signal and resample the data. After analyzing the typical structures of the clock and data recovery circuit, this thesis has designed a 20Gb/s full-rate Bang-bang type CDR applied to the high-speed SerDes, which lock fast and has a small output jitter.In modern high-speed SerDes communication system, with the increasing transmission rate, the received signal is affected by serious inter-symbol interference (ISI) due to non-ideal factors, such as dielectric loss, crosstalk, and dispersion. ISI will not only increase the error rate of the system, and even make the clock and data recovery circuit cannot extract the clock signals correctly. Therefore, an equalizer circuit must be used to compensate for the channel loss. The common transmission medium channel characteristics have been analyzed in this paper firstly. After discussing the principle and typical structure of the receiver equalizer, we propose a feed-forward equalizer (FFE) which can be applied in the 20Gb/s high-speed SerDes. With 3 tap fractionally spaced delay lines, this feed-forward equalizer can compensate for the long-term transmission loss.This design is based on TSMC 65 nm COMS GP process and the chip area is 1190μm×810μm including feed-forward equalizer and clock and data recovery circuit. The post simulation results show that the EQ circuit can equal the signals affected by ISI and eye-diagram after equalizer can be opened to 0.76UI. The equalized signal used as the input of the CDR and the capture time of the CDR circuit is less than 100ns. The recovered 20GHz clock exhibits a jitter of 2.25pspp, and the recovered 20Gb/s data exhibits a jitter of 3.3pspp. The whole dissipation is 128mW when the supply power is 1V.