| With the rapid development of the integrated circuit industry,high-speed data interfaces become more and more important.Ser Des,a serial interface device for high-speed communication,has been applied to many aerospace equipment,and it is very important to transfer information correctly in the space radiation environment,for which the study on radiation characteristics of Ser Des should raise more concerns.To meet the requirement above,a high-performance,anti-SET equalization and sampling module for Ser Des receiver based on 40 nm CMOS process are developed in this thesis,the analysis and reinforce of single-Event transient effect in equalization,sampling module,offset module and analog front end are focused on especially.Firstly,the non-ideal characteristics of the transmission line are analyzed according to the transmission line model in this thesis.The reasons of transmission loss caused by the non-ideal characteristics,the radiation effects in the space radiation environment,and the influence of radiation effects on the Ser Des circuit are studied.Secondly,the equalization and sampling module are realized in this thesis,the offset module and analog front-end are designed at the same time.The potential sensitive nodes are chosen in order to analysis the influence of SET in these modules according to the results of the simulation.Different simulation methods are selected according to the characteristics of the circuit.For example,the sensitive nodes are simulated and analyzed under different control situations.When the circuit is symmetric,the single-side circuit is simulated.For the sampling module,the time of SET occurrence should be analyzed by scanning.Finally,according to the simulation results,this thesis reinforces the sampling module and implements the layout of digital-analog circuit which has already reinforced.The layout implemented in this thesis meets the requirements of eye diagram and at the same time,the drive and delay of the circuits are satisfied.According to the results of SET sensitivity simulation and analysis in high speed equalization and sampling module based on 40 nm CMOS,the equalization module is not sensitive to the SET due to its special characteristics,while the analog front end and offset module have the characteristics of anti-set because of its simple circuit structure.However the sampling module is sensitive to SET,for which the method of three-mode redundancy is used to reinforce the sampling module.The layout of the circuit after reinforce is implemented and the parasitic parameters are extracted for post simulation.Post simulation results show that the circuit can realize the functions,and the eye width of the output signals of the equalization module remains at 0.8UI.The transmission rate reaches 6.25 Gbps.The sampling module can sample data correctly under SET,while the layout area remains the same. |
