A High-Performance, Low-Power ∑△ Analog-to-Digital Converter

In 2006's "The development outline of long-term national science and technology(2006-2020)" which determines the next 15 years striving to achieve a major breakthrough in the 16 special science and technology programs,the first is the key electronic devices,high-end general chips and basic software.The research work of high-end general purpose ICs as well as owning China's independent intellectual property rights is very important to improve the whole compete ability of China's IC industry.High-end general purpose ICs,such as analog and mixed-signal ICs,require a relative high technical threshold.On the other hand,as the rapid development of China's multi-media digital audio-video SOC chip,the industry itself has urgent demands of an independent CMOS based,high-performance and low-power analog-to-digital converter(ADC). Based on the backgrounds above,the purpose of this paper is to implement a high-performance, low-power audio ADC with comparative performance with international similar products.Σ△modulation is a promising solution to implement high-resolution ADCs in VLSI technology,for the never-ending thirst for high fidelity digital audio.Combining oversampling and feedback to shape the noise,and using a digital lowpass filter to attenuate the noise that has been pushed out-of-band,it is possible to achieve a resolution as high as 16bit plus.This approach is relatively insensitive to imperfection of circuit components,providing numerous advantages for the realization in high-density and low-cost modern VLSI technologies.Further more,Σ△architectures are a potentially power-efficient means of implementing high-resolution ADCs.This work is devoted to the research and realization of a high-performance low-powerΣ△ADC.The main contents and innovative points of this dissertation are listed below.Firstly,intensive study is given to the non-idealities for the electrical implementation and the impact of these error mechanisms.The importance increases when the specifications of theΣ△modulator are demanding because they can become the dominant error sources.The power of each error induced by non-ideality is derived in closed form through the theories analysis, thus it is important and necessary to select the most appropriate modulator topology and put much effort in optimization so that the design of the circuit blocks are more targeted.Secondly,system-level optimization is performed on a 2-1 cascaded modulator topology,in order to provide a favorable set of design trade-offs for high-performance,low-power operation. The 2-1 cascaded architecture achieves third-order noise shaping with relatively modest constraints on device matching,and especially avoids stability issue which is commonplace in high-orderΣ△modulator topologies.The implementation of this architecture provides a higher overload level,close to the full scale range,which allows reduction in the sampling capacitance for a given specification.Therefore it is especially true for low-power,high-performance design. Employing coefficients optimization and signal scaling,the high-performance design becomes rather practical.Behavioral simulation provides an efficient means for system level verification. Its function includes from system level design to circuit blocks synthesis under some key performance constraints.Thirdly,the high-resolution,low-power 2-1 cascaded modulator is realized employing switched-capacitor in standard CMOS technology.A power-efficient class A/AB operational transconductance amplifier(OTA) is proposed,which achieves high slew rate of 100V/μs with only 0.8 mA current consumption.Scaling integrator sampling capacitors down to minimum value required by KT/C noise at each stage is another kind of effective method of reducing power dissipation.High-linearity sampling is achieved with a novel bootstrapped switch which offers great attenuation of the sampling distortion.A low-power regenerative comparator is used as the single-bit quantizer.A reference current source with high power supply rejection ratio (PSRR) and a multi-phase clock generator are also included.Fourthly,an area-efficient decimation filter for theΣ△modulator is also presented.The filter design toolbox in MATLAB greatly simplifies the filter prototype construction.In this filter,a multi-stage structure is adopted and the "multiplication-accumulation" is designed using serial method,which facilitates hardware implementation.The decimation filter verified with FPGA achieves 0.001 dB passband ripple and 100dB stopband attenuation,which adequately meets the requirements of high-end audioΣ△ADCs.Finally,a monolithicΣ△ADC is implemented in SMIC 0.18μm CMOS process including aΣ△modulator and a digital decimation filter.The experimental prototype achieves a dynamic range of 93dB and signal to noise-plus-distortion ratio of 88dB over a 22.05 KHz bandwidth. The performance of some recently reported designs by mainland research organizations is compared.It is evident that the design in this work has competitive power efficiency.The objective of this study is to demonstrate an audioΣ△ADC chip fabricated in standard CMOS technology and design relative constituent circuit IP's.The successful chip realizes a high performance audioΣ△ADC totally with our own property rights.The verified design flow of mixed-signal chips,from theoretic analysis,system level optimization,circuit design to experimental prototype,makes good preparation for future development.