Embedded-Pipelined Analog-to-Digital Converter

An analog-to-digital converter acts as the input part of the digital processor on natural signals. The performance directly limits and influences the performance of the whole system. So for a good system it is very important to design a required analog-to-digital converter. There are multi schemes in analog-to-digital converter design, in them pipeline structure is popular in high performance a/d converter design because every stage of pipelined a/d converter can be realized by switch-capacitor circuit, so it's structure is very simple and fit of CMOS techniques. It has been an important subject to realize high performance pipelined a/d converter in recent years.Based on detailed analysis of the popular structure of 1.5bit per stage in pipelined analog-to-digital converter, the dissertation focuses on switch-capacitor sample/hold circuit design and digital correction circuit design, designs a 10bits/20MSPS pipelined analog-to-digital converter. The innovative points and results of the work include:1. Digital correction circuit used to prevent comparator offsets from limiting the resolution of an analog to digital converter. In this technique, the comparator offsets are not corrected. Instead, the analog-to-digital converter is designed in a way that is tolerant of comparator offsets. Without digital error correction, the comparator offset must be no more than the least significant bit of the analog-to-digital converter. With digital error correction, larger offsets can be tolerated. This technique is attractive because it allows the use of simplified comparators. This can potentially save hardware and power. This technique also allows analog to digital converter to achieve resolutions that would not be possible without it The digital correction circuit in the dissertation is realized through a simple shrift register and logic gates.2. In the dissertation, in order to make the circuits simpler, the input signal and the SUB-DAC analog outputs are multiplied by a factor of 2 before the SUB-DAC analog output is subtracted to obtain the residue.3. A 10-bit 20MSPS pipelined analog-to-digital converter and layout are researched deeply and designed by the CHARTERED 0.35um double-gate four-metal CMOS process. The chip consumes 253mW, at 5V supply. An 8-bit 20MSPS pipelined analog-to-digital converter is taped out via MPW, and the chip occupies 1.8×1.7mm~2. The chip and part components have been evaluated.