The Design Of 12 Bit Pipelined A/D Converter

In this thesis, a 12bit, 50MSPS, 1V input range, single 3.3V supply, pipelined ADC is presented.First the architecture and the theory of several popular ADC is presented, the advantage and the disadvantage is analyzed. Then the basic architecture is designed, the architecture consists of a front end SHA followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4bit first stage followed by six 1.5bit stages and a final 2bit flash.The design is begin at the system architecture, the function is analyzed firstly, then educe the arithmetic, the circuit is based on arithmetic. The SHA used overturn architecture. Each stage of the pipeline, excepting the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and inter stage residue amplifier (MDAC). The encoder and the correction logic consists of logic circuit.The simulation results with Hspice and TSMC 0.35um CMOS process proves it can carry out the basic function, the last 4bit of the digital outputs is imprecise.