.3 G Receivers Adc In The Mdac Module

In this paper, according to the system requirement of ADC for 3G recever, the influences of MDAC to the system are considered. The CFCS (Commutated feedback-capacitor Switching) technique is analysed. The total MDAC is designed using the CFCS technique and the Capacitor scaling down technique.In order to get high-resolution, choosing different capacitor as feedback capacaitor in the amplification cycle of the residue amplifier according to different input signals. CFCS technique relaxes capacitor matching requirement for manufacturing technology, and improves system linearity.In order to get high-speed, the architecture of folded gain-boosting OTA is used as the residue amplifier. To make the system stable, the Switched-capacitor type and the continuous-time type common-mode feedback circuits are designed for the main op amp and the two auxiliary op amps respectively.Based on the TSMC 0.35μm/3.3V silicon CMOS process model, every MDAC has been simulated in Cadence simulation environment. The results show that, for the OTA in the first-stage MDAC, DC gain is 102dB, gain-bandwith is 1.01GHz, phase margin is 64o, power consumption is 36mW. the first-stage MDAC reaches settling final value of 499.69mV, slew rate of 520V/μs and settling time of 4.3ns.Therefore, these MDAC can reduce capacitor mismatching error by adopting CFCS technique, and can save power consumption further by adoping Capacitor scaling down technique.They can fulfill the system requirement of 14b 100Msps pipeline ADC.