Research And Design Of MDAC Based On Pipeline ADC

With the rapid development of computer, communication and multimedia, the extent of digitalization of the high-tech in the global has been continuely deepened. The increase of digitization and integration in semi-conductor technology has considerably promoted the development of analog-digital converter tech towards high precision, high speed and low power dissipation. In order to meet the requirements for ADC in the application, a 1.5bit/stage MDAC circuit is presented, which is to be used in a 12-bit pipeline ADC under 50Mbps.In this paper, MDAC, the kernel module of the pipeline ADC, is researched. In SC circuit, the mismatch between capacitor is the main error source. Thus, this paper introduces a method called Capacitor Error Averaging Technique, which could effectively reduce the negative influence caused by capacitor-mismatch.The circuit is designed with the technology of IBM 0.13um CMOS process. The range of the input voltage of MDAC is±0.8V and power supply is 1.5V. The folded-cascode structure is used to design the principal operational amplifier. In order to enhance the DC gain, the gain boosting technique is adopted. Under the simulation in Cadence Spectre, the DC gain of the principal operational amplifier could reach 107.6dB, and the unit gain bandwidth is 448MHz. The setup time of the signal of the whole MDAC circuit is approximately 7ns, which meets the requirement of 50MHz -sampling rate, the layout area is 91um×103um.