Research And Design Of 12-bit High Speed Pipeline ADC

With the development of communication technology,the conversion of analog signals and digital signals gradually becomes a key module restricting the performance of a system.Hence,it becomes more and more important of the design for a high speed ADC.Because the pipeline structure can be achieved by dividing a high precision system into a plurality of low precision modules,and achieve high speed.So this paper uses pipeline architecture to realize a 12bit high speed ADC.In this paper,the high speed and high precision Pipeline ADC is studied.And a 12-bit 500MSPS high speed ADC is designed based on 65nm technology.Firstly,this paper introduces the principles and performances of pipeline ADC.Secondly,the potential errors of each key module are analyzed,and the parameters of each device are determined.Lastly,this paper uses the architecture of the pipelined ADC with redundancy correction as 1.5b*3+2.5b*3+3b.The operational amplifier is the core module of a pipelined ADC,and it is one of the main modules of the performance of ADC.This paper adopts two grade structure to achieve high gain and high bandwidth,which is used in the first stage with the structure of Gain-boost folded cascode structure to achieve high gain,and the second stage with the common source amplification to achieve high output swing.The high bandwidth is achieved by improving the transconductance of the input transistor.In order to reduce the error caused by nonlinear switch resistance,this paper adopts bootstrap switch circuit with substrate adjustment.The gate-source voltage of the switching transistor is kept constant,witch reducing the nonlinear sampling switch,and improving the precision of the ADC.In order to ensure the signals which input to the MDAC circuit and sub ADC circuit are s ynchronous,the charge redistribution sampling and holding circuit is adopted in this paper.This paper uses 65nm CMOS technology to complete the circuit schematic and layout,and complete the pre simulation and post simulation by the Cadance Spectre simulation software at 1.2-V supply.The simulation results show that the gain of the amplifier in the sample and hold circuit is 90dB,the unit gain bandwidth is 5GHz,and the phase margin is 63°When the sampling rate is 500MSPS,the input sinusoidal signal is 250MHz,the effective number of bits(ENOB)for the system is 10.58bit,the Signal to Noise and Distortion Ratio is 65.45dB,the differential nonlinearity is 0.8LSB,the integral nonlinearity is 1.2LSB,and the power consumption is about 190m W,which meet the design requirements.