The Research And Design Of MDAC Of High-speed And High-Resolution Pipeline ADC

Analog-to-Digital Converter (ADC) is a key block, which links the analog world and the digital world. With the development of the wireless communication, High-speed and High-resolution ADC will play a more important role in high speed analog signal process. Compare with Flash ADC、Successive Approximation ADC (SAR)、 Sigma-Delta ADC and so on, Pipeline ADC has been generally more preferred as a good compromise between speed and resolution.As a crucial component of the Pipeline ADC, Multiply Digital-to-Analog Converter (MDAC), which has direct impact on the resolution and speed of the system, occupies the most of the area and power of the ADC. How to distribute per stage resolution and how to realize the circuit is a hot issue for the design of high-speed and high-resolution pipeline ADC.Firstly, the thesis explains the theory of the MDAC module; By analysis the resolution、speed and noise, the architecture has been determined; secondly, the sampling capacitance has been optimized to reduce the power consumption; then, the architecture of the sample and hold(S/H) Circuit has been definition by comparing the two common architecture; in the end, the related indicators has been obtained. The main works and innovation in this work are:1) The noise model of MDAC has been deducted, which gives the quantitative analysis. 2) Make an quantitate analyses on the 2.5bits/stage.3) Make an improvement on the Auxiliary Amplifiers to meet the demands of high resolution.This ADC is implemented in 0.13um 1-Poly 8-Metal CMOS technology. Every MDAC has been simulated in Cadence simulation environment. The results show that when the sine wave@99.21875MHz is give, the SFDR of first-stage MDAC reaches 92.4567dB, which meets the requirement of 14-b linearity; The Spurious Free Dynamic Range (SFDR) of MDAC2 and MDAC3 are 78.7dB、70.24dB,which also meets the requirement of linearity and verified the correctness of theoretical derivation.