Design Of High-Resolution And Low-Power Pipeline CMOS Analog To Digital Converter

With the development of communication networks and Internet of things, wireless communication systems are needed more and more. Low-power UHF RFID technology in this context, has become a research hotspot. RFID technology with the advantages of low power consumption, high speed and low cost in networking, communications, digital video signal processing and high-speed Ethernet has broad application prospects. Based on high-speed, low-power goals of RFID systems, this article designs a high-resolution and low-power ADC with high sampling rate.This article is designed with pipelined ADC configuration to meet the high sampling rate and low power design requirements. In this article, detailed analysis of the circuits in the pipelined ADC modules and performance limiting factors are conducted, including gain-boost OPAMPs, the bootstrapped switch, dynamic comparators and the stable reference voltage of the bandgap circuits and linear regulator. In pipelined ADC circuit configuration, this article chooses the 1.5bits/stage structure with the extra redundancy bit to achieve the self-calibration function of pipeline ADCs. By using OPAMP sharing and scaling down technique to reduce the number OPAMPs and load capacitance of OPAMPs, the power consumption is much reduced. For the design of OPAMP sharing configuration, the sample and hold circuits shared the same OPAMP with the first-stage residual gain circuits. The following eight stages shared four OPAMPs between adjacent two stages. The last two bits are quantized by a flash ADC.This article also analyzes the supply stability and temperature compensation, so that the power supply range can be set between 2.0V to 3.3V. The low-drop linear regulator output is stable at 1.8 V.The pipeline ADC is implemented in TSMC 0.18μm 1P4M process at 1.8 V supply. The performance specifications are 11 bits resolution and 100MS/s sampling rate. The pipeline ADC’s power consumption and area are reduced and optimized by OPAMP sharing technique. Optimized bootstrapped switch is used for the improvement of linearity and resolution, and gain-boost OPAMP is designed for the high gain. The proposed pipeline ADC only occupies a core area of 0.65mm2 and dissipates 52 mW from 1.8V supply. The circuit achieves an SFDR of 78dB, an SNDR of 66.6dB and an ENOB of 10.8 bits at an input frequency of 10MHz under 100MS/s sampling rate.