Design Techniques For High-speed And Low-power SAR ADC Based On 65nm CMOS Process

As the digitization of modern electronic systems increasing, A/D converter, the bridge between analog and digital signals, plays an increasingly important role in many fields and has become one of the most important parts of the electronic information technology. With the rapid expansion of low-pwer electronic systems, such as wireless sensor nodes, portable consumer electronics and wearable medical devices, the demands of the high-speed and low-power ADCs with high integration density are increasing. So the advanced manufacturing technologies are adopted to meet the huge market demand, and the 0.35?m-0.18?m technologies are displaced by 90nm-32 nm technologies. Successive approximation analog-to-digital converter(SAR ADC) has become the main direction of the research in Nanoscale processes, because of the advantages of simple construction, small die area and good compatibility with digital systems under advances peocess. Therefore, it is very important to study and design a high-speed and lower-power SAR ADC under 1.2V 65 nm CMOS process.The research goal and research contents are determined by the analysis of research status of high-speed and low-power SAR ADC. Then, the working principle and basic structure of SAR ADC are introduced. The swithing energy, capacitors' mismatch and energy-efficient switching schemes is explored with theoretical derivation and verified by modeling using Matlab. The effects for the performance of SAR ADC are studied on analysis of the offset, noise and steady-state error of dynamic comparators. And the SAR logic implementation technologies are analyzed.Based on the 1.2V 65 nm CMOS process, a 10-bit 80 MSPS asynchronous SAR ADC is designed. A new energy-efficient capacitor switching schmeme with less approaching steps is proposed to reduce the power consumption. And binary-scaled error compensation, which makes SAR ADC have the fault-tolerant capacity, is adopted to improve the speed. Then a bootstrapped switch with high linearity is designed by using bootstrapping technique. Without any increase in power consumption, a low-power dynamic comparator is designd by extending the time of amplifier stage. An asynchronous SAR logic with bypass mechanism and a capacitor-swithing logic are proposed to cooperate with the submoduar circuits to implement analog-digital conversion. A digital error circuit with overflow correction is simplified by optimizing the algorithm of binary-scaled error compensation, and it converts 12-bit redundant code to 10-bit binary code.Based on the 1.2V 65 nm CMOS process, the layout of this SAR ADC is designed. At 1.2V supply voltage and 80 MSPS, the post-simulation results shows that the SAR ADC achieves a SFDR of 72.5dB, a SINAD of 59.67 dB, and it only consumes 0.87 mW with a FOM of 13.8 fJ/conv.step. So the SAR ADC in this thesis achieves characteristics of high SFDR, high SINAD and low power, and the FOM has reached the domestic leading level.