High-speed low-power asynchronous circuits |
Posted on:2005-06-12 | Degree:M.Eng | Type:Thesis |
University:McGill University (Canada) | Candidate:Saadallah, Nisrine | Full Text:PDF |
GTID:2458390011450577 | Subject:Engineering |
Abstract/Summary: | |
This thesis presents several design experiments for high-performance power-efficient asynchronous circuits.; In Chapter two we present a new asynchronous pipeline logic family with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. An implementation in 0.18mum CMOS exhibits a latency of 56ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in Hspice simulation.; We also present the design of a low-control-overhead asynchronous microprocessor integrated with a high-speed sampling FIFO. This is an experiment in exploring the benefits of asynchronous design in high-speed embedded DSP applications. It reports on the design approach, implementation and performance, including a comparison with the synchronous version of the microprocessor. |
Keywords/Search Tags: | Asynchronous, High-speed, Pipeline |
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