Analysis And Compensation Strategy Of Current Source Matching Error In High-Speed CMOS DAC

Nowadays, digital-to-analog converter (DAC) plays a very important role in the modern digital and analog circuit. The fast development of computer technology, digital processing technology, and microelectronic technology contributed to the continuous advancement of digital-analog conversion, and at the same time, DAC has become the main factor to restrict the development of the computer, communication and DSP, and has become the key to improve signal processing speed and accuracy, so that a greater demand is created for the speed and precision of DACs.Using the INL_Yield Model, this paper derives the relationship between DAC resolution and random error. The minimum size of the current source is fixed by the allowed random error, which can compensate the random error. In addition, various common gradient error compensation programs are discussed systematically, and an approximately completely random switching order is proposed, called Q2-RW Switching Scheme. It takes full account of current source switching random and matching error by environment factors, and for any error distribution, linear or nonlinear error could be reduced effectively.Based on the analysis of current source matching error and Q2-RW switching scheme, and under SMIC0.18μm 1P6M CMOS process, this paper proposes a 12-bit 1GSPS segmented current-steering DAC, and its segmented form is 5+3+4. The simulating results show that, the integral nonlinearity error and differential nonlinearity error are both within±0.5LSB; when the input signal frequency is 480MHz, and sampling frequency is 1GHz, the Spurious-Free Dynamic Range is 76.2dB and the Effective Number of Bits is 11.5. These indicate that this DAC has a good dynamic range and good accuracy, and also prove the effectiveness of the error compensation strategy.