Research And Design Of A 12 Bit 100MSps Low Power Consumption SAR ADC

In order to adapt to the rapid development of wireless communication,wearable equipment,high-speed digital signal processing and other fields.As the interface bridge of analog signal and digital signal,analog-to-digital converter(ADC)in high-speed,high precision and low energy consumption research will become more important.Due to the high-performance ADCs are limited in speed,accuracy and energy consumption,especially in the case of process size and power supply voltage reduction,the small size effects of the device are more prominent,and the advantages of the high-speed ADC architecture of the traditional analog domain are obviously reduced.In order to make full use of the advantages of advanced technology line and cooperate with high-speed digital circuit,and with theoretical analysis and modeling verification,a 12-bit 100 MSps single channel SAR ADC which applied to ultra-high-speed interleaved ADC base on standard 40 nm process was implemented.First of all,this thesis uses a non-binary capacitor array architecture and a smaller unit capacitance value,only need to establish the reference level in the redundant range can be greatly reduced the establishment of time.With the auxiliary DAC cooperation,the DAC placed the theoretical value of the reference level in the middle of the redundancy interval,making the ADC can tolerate positive and negative deviation of the reference level error.In addition,the dynamic power consumption can be reduced due to the use of smaller DAC capacitor value.Second,non-binary capacitance array redundancy can tolerate quantization error of SAR ADC,the first five bits of the ADC using single-stage latch comparator quantization,the last eight bits using pre-amplifier + latch for quantization,these two different precision comparators working in time-sharing mode,can effectively reduce the power consumption of the first several bits,and the high-precision comparator will be power down after the completion of the entire quantization cycle can also reduce the static power consumption.The large input signal will not be amplified when the first several bits are quantified by single-stage latch comparator,this will also reduce the comparator comparison delay.Finally,the SAR logic circuit uses a new latch-type structure,with the use of asynchronous timing logic,data storage and coding delay compared to the traditional trigger logic delay greatly reduced,at the same time,this thesis also uses the technique of direct coding that the comparator output results without latch,which reduces the time delay of data storage in SAR logic units.Based on the standard 40 nm process,the circuit and layout were designed carefully,the parasitic parameters of this design were extracted and the circuit was simulated for the overall performance verification.At the sampling frequency of 100MS/s and the input signal is close to the Nyquist frequency,the SFDR,SNDR and ENOB of the designed SAR ADC are 83.63 dB,72.98 dB and 11.83 bits respectively,The total power consumption of the SAR ADC is 6.1mW,resulting in a FoM value of 16.8fJ/conv and the area of core layout is 0.018mm~2.Finally,the channel SAR ADC was applied to ultra-high-speed time interleaved ADC which was fabricated on the standard 40 nm CMOS process for wafer verification,the test results show that the maximum and minimum values of DNL are 1.08 LSB and-0.864 LSB respectively;The maximum and minimum values of INL are 3.76 LSB and-0.48 LSB respectively and the SFDR and SNDR are 74.68 dB and 62.32 dB respectively,the ENOB reaches 10.06 bit.