Research On High Resolution Low Power SAR ADC

Analog-to-Digital Converter(ADC)is an essential part of almost every complex integrated circuits.In recent years,the rapid development of wireless communication provides extraordinary opportunities for the application of ADCs.Based on advanced semiconductor manufacturing processes,the successive approximation register(SAR)ADCs which consist of many digital modules have achieved great improvement in performance.With the improvements in speed,accuracy and power efficiency,SAR ADC stand out from many ADC structures.It is of profound significance to study high performance SAR ADC to meet the requirements of low power consumption,high quality wireless communication.The current research of SAR ADC both at home and abroad are investigated,several common structures of the ADCs are also introduced in this paper.Eventually,a fully differential charge redistribution SAR ADC is adopted.A MATLAB behavior model of the designed SAR ADC is established to analyze several nonideal factors.In order to improve the linearity of the sampling switch,a bootstrapped switch is adopted.The DAC area and power consumption are greatly reduced by using segmented capacitor array.A binary-scaled recombination weighting method is used in the DAC without adding extra capacitors.The DAC settling problem is alleviated and the wrong decisions made during the conversion are corrected.Besides,a correction technology is developed to mitigate the effects of parasitic capacitance in the capacitor array.The linearity of DAC is improved without using additional circuit or conversion cycles.The DAC uses a partially monotonic switching scheme,and the power consumption is reduced by 50% compared with the monotonic switching scheme.At the same time,the common mode voltage variation of DAC output is also reduced by half,alleviating the dynamic offset of comparator.The high precision and high speed comparator designed in this paper adopts a two-stage preamplifier and a dynamic latch comparator to reduce the offset and delay.Monte Carlo simulation shows that the offset voltage is 0.85 m V.The SAR logics transmits the DAC output to the switch control terminal directly,reducing the critical path delay and accelerating the conversion rate.The entire circuit layout is completed using SMIC 55 nm CMOS process and core layout area is180?m×140?m.Post-system simulation results show that: SNDR of 80.7d B and SFDR of 86.1d B are achieved with a Nyquist rate input at the sampling rate of 50Ms/s,and the power consumption is 7.6m W.