Design Of An 8-bit High-speed Low-power SAR ADC

Modern high-speed communication systems such as ultra-wideband radios,high-speed serial links,and Ethernet network transceivers demand medium-resolution analog-to-digital converters(ADCs)with hundreds of MS/s.In contrast with flash and pipeline ADCs,successive-approximation-register(SAR)ADC is widely used due to its simple and compact architecture,low power,well-adapted in advanced processes and easy-interleaved advantage.The main task of this thesis is to design a high-speed and low-power asynchronous SAR ADC with8bit resolution which meets the requirements of above mentioned modern high-speed communication systems.2-then-1bit/cycle SAR ADC architecture is adopted.This thesis takes both high-speed and low-power design into consideration while guaranteeing high ENOB performance.Firstly,three comparators and two capacitive digital-to-analog converters(DACs)are implemented to perform first four2bit/cycle conversions,which significantly improve the speed of ADC.Secondly,only center-comparator is used in the last 1bit/cycle phase where is noisy,which should have better noise performance.By optimizing the power of the three comparators,the overall power can be effectively reduced while ensuring that the ADC has better ENOB performance.Thirdly,to reduce the relative offset error between the three comparators,a low-power on-chip background offset calibration for outer-comparators is proposed,which is performed at a low frequency in the last 1bit/cycle phase,keeping track of the voltage-temperature variations and achieving high-energy-efficiency.Becides,there is only one binary redundant bit in the system due to larger LSB to offer enough redundant range for both DAC settling error and mismatch between DACs,which simultaneously reduce both total cycles and the overhead of digital error correction circuit.Finally,the proposed center-comparator-based asynchronous self-time control scheme with two step acceleration further compresses conversion time,improving the maximum speed of ADC.The presented SAR ADC is implemented in TSMC 40nm CMOS process,which occupies an active area of 0.016mm~2 including on-chip offset calibration circuit.Post-simulation results show that the ADC exhibits a 7.6bit ENOB at Nyquist input frequency when operating at a sampling rate of 400MS/s under a1.1V supply,leading to a FoM of 56.3fJ/conv.-step.Moreover,the ADC achieves a 7.6bit ENOB at Nyquist input frequency and a FoM of 64.2fJ/conv.-step when operating at 500MS/s under a 1.25V supply.Consequently,the results meet the high-speed and low-power design requirements.