| The successive approximation register analog-to-digital converter(SAR ADC)is widely used in wireless communication and portable instrument industry because of its small area and low power consumption.With the development of CMOS technology and the improvement of devices'speed,the demand for high-speed SAR ADC is increasing.Researchers domestic and abroad have proposed many new technologies to improve the speed of SAR ADC,among which time interleaved technique and asynchronous clock control skill are widely used in the design of SAR ADC.Some compensation techniques for capacitor arrays can also improve the speed of the ADC and reduce the overall power consumption.Firstly,the capacitor switches'procedure and the redundancy compensation methods of DAC capacitor arrays are deeply studied.The structure and performance of DAC capacitor array have the greatest influence on the overall accuracy,speed and power consumption of SAR ADC system.By analyzing and comparing the difference between the average switching power consumption and speed between the conventional capacitor switching procedure and the monotonic capacitor switching procedure,it can be concluded that the average switching power consumption of the latter is lower and the speed is faster.The principles of non-binary redundant compensation method,the binary-scaled redundant compensation method and the binary-scaled redundant recombination method were introduced in detail,and with all these three methods used in the design of 10-bit SAR ADC,the comparison of their design difficulty and total building time shows that the circuit of binary-scaled redundant recombination method can be designed easily than that of non-binary redundant compensation method,and the total building time with the capacitor DAC of binary-scaled redundant recombination method is shorter than that of non-binary redundant compensation method,so the former method is used in this high-speed SAR ADC.By analyzing the working principle of the two-stage reference method of capacitor DAC,it is concluded that the area and power consumption of SAR ADC can be further reduced in this method.It shows that the system speed can be greatly improved and the power consumption can be further reduced by combining the monotonic capacitor switching procedure,the binary-scaled redundant recombination method and the two-stage reference method in one high-speed SAR ADC system.In order to transform the 12-bit digital codes into 10-bit ones,a digital logic calibration circuit is designed according to the structure of the final capacitor DAC.Secondly,the high-speed dynamic latching comparator and the SAR logic control circuit are further studied.The circuit of the former is improved to speed up the charging and discharging speed of the output node,so the comparison and reset speed are increased.For the SAR logic control circuit,in order to ensure that the accuracy of the SAR ADC meets the requirements,the traditional circuit structure is still used to control the timing step,but for the control circuit of capacitor DAC,a dynamic latching structure is used,mainly to further reduce the power consumption of the system.Finally,in order to further improve the overall speed of the SAR ADC,the time interleaved technology is studied.The main factors influencing the ADC performance of time interleaved SAR,especially the clock deviation,are deeply analyzed.The advantages and disadvantages of phase locked loop(PLL),delay locked loop(DLL)and clock frequency divider are analyzed and compared,and it is believed that the clock frequency divider occupies smaller area and consumes less power,and it also can be designed easily.On the basis of the above key technologies,this paper designed a 10-bit 320MS/s SAR ADC.The design uses TSMC40nm CMOS process,under the sampling frequency of 320MS/s and the Nyquist input frequency,the overall power consumption obtained by post-simulation of the circuit is about 2.2m W,SNDR is about 55.2d B,and ENOB is about 8.9.The total area of the ADC is about0.031mm~2. |
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