High Speed And Low Power Successive Approximation ADC Design

With the rapid development of digital intelligence in the electronic information industry,the widely use of devices such as computers and digital communications has gradually formed a pattern with digital systems as the main body.However,what people generally see is still a continuously changing analog quantity.Analog-to-digital converters(ADC)convert analog signals into 0/1 digital signals,which are important modules in industries such as data collection and data processing.Based on the needs of high-speed data transmission applications including wireless display and fast upload/download of media content,this paper studies the design of SAR ADC with high sampling rate and low power consumption.This paper investigates the research results of SAR ADCs with high sampling rate and low power consumption at home and abroad,and analyzes the basic principles of SAR ADCs with several common structures.The high sampling rate and low power SAR ADC designed in this paper includes a differential DAC capacitor array,a comparator,and a successive approximation logic circuit.The paper adopts a bootstrap switch,uses a binary capacitor scaling and recombination strategy and monotonic capacitor switching timing.The number of unit capacitors is reduced by half compared with traditional capacitor timing capacitor arrays,and power consumption is reduced by 81%.A two-stage dynamic comparator is adopted.The asynchronous self-controlled successive approximation logic module is adopted,which effectively improves the conversion rate.Finally,based on the TSMC 40 nm CMOS process,the design and performance simulation of each key unit circuit of the overall ADC is completed.Simulation results show that at a supply voltage of 1.2V and a sampling frequency of 80 MS / s,the ADC's SFDR is 76.99 d B,SNDR is 60.13 d B,ENOB is 9.70 bit,power consumption is 0.93 m W at 1.2V supply voltage.