Study Of High-speed And Low-power MPSoC Arbiters

With the development of semiconductor technology, an increasing number of functional circuit modules can be integrated onto a single chip. MPSo C based on bus becomes the main way because of its low cost, short design cycle, easy reusability, small size, high speed and low power. However, multiple IPs make communication by bus, thus extra power and speed loss will be caused by bus contentions, which degrades performances of MPSo C. It is important that to avoid “starvation” and “monopolization”, novel arbitration algorithms of MPSo C should be worked out according to its working conditions to deal with bus contentions. From the hardware perspective, asynchronous circuits have advantages of high speed and low power in particular circumstances, thus GALS(globally asynchronous locally synchronous) is deployed. Different functional modules in MPSo C arbiters are designed in synchronous and asynchronous way respectively according to the working circumstances. Performances of smaller area overhead, high throughout, high speed, low power and high bandwidth utilization are achieved under the premise that arbitrations are made correctly. In this paper, researches are made on arbitration algorithms and arbiters. Achievements are as follows:1. Researches are made on design methods of asynchronous circuits and Balsa-Xilinx automatic design method is established. Advantages and disadvantages are compared among different design methods. Automated digital design methods are studied in detail. Module library of asynchronous circuits is set with multiple digital design methods and their advantages and disadvantages are obtained. Asynchronous design and verification flow is established: Balsa-Xilinx design method.2. Researches are made on two-level arbitration algorithm and there are obvious improvements in output bandwidth allocation. The two-level arbitration algorithm is designed by combing advantages of traditional arbitration algorithms. It sets weight by tickets and employs improved Fixed Priority(FP) and RR arbitration to work in turn respective ly under the conditions that there is no contention and there exit heavy contentions. The proposed arbitration algorithm is much better in the output bandwidth ratio, bandwidth utilization, power and it also has advantages in speed and area.3. An adaptive and weighted dynamic arbitration algorithm is proposed. At the beginning of each arbitration cycle, the proposed arbitration algorithm checks working environment, then requests can be changed correspondingly to achieve quick response or complicated bandwidth allocation. Arbitration can be accomplished when combing the advantages of RR and FP arbitration algorithms. It has better bandwidth allocation and bus utilization is improved and bus utilization is increased by 11.3%-56.3%.4. Research on asynchronous adaptive and weighted dynamic arbiter with four-phase and dual-rail protocol. This protocol can avoid extra dynamic power when there is no valid requests, thus the accuracy of bandwidth allocation is improved. Static power can be reduced in arbitration circumstances with dual rail. High speed and low power are achieved with relative area overhead: speed is increased by 18%-50.4%, dynamic power is reduced by 8.3%-46.2% and static power is decreased by 81.8%-90.9%.5. Research on GALS lottery arbiter based on traditional lottery arbitration algorithm. The lottery decision mechanism deploys four-phase dual-rail protocol to avoid the loss of tickets, and it utilizes cross parallel working manner of asynchronous pipeline to improve the working speed. It has smaller area overhead and better bandwidth allocation. Speed is improved by 49.2%. High speed and low power is achieved.6. Based on Busmatrix, which is one of the advanced high-performance n-of-n buses, a high-speed and low-power round-robin arbiter is proposed. By combining the advantages of mask-vector arbitration algorithm and RRA-2pick-Oz U arbitration algorithm, the complexity of the algorithm is optimized. Required data communication is made through four-phase dual-rail protocol. Furthermore, speed is increased by 16.7%-53.9%, throughput is improved by 13.9%-77.2% and power is reduced by 61.8%-71.8%. High speed and low power are achieved when throughput is large.Research can be applied in VLSI high speed and low power implementation and optimization. It provides new ways for performances of MPSo C and design method of asynchronous circuit and has important academic significance and application value.