Research On The Design Technology Of Low-voltage Low-power Analog To Digital Converter

With the developing of the Integrated Circuit technology and the minishing of the device size, the electronic system in future must be the application of the System-on-chip (SOC), which is also a mixed signal system. It needs integrated digital circuits and analog circuits together in a single chip with aims to reduce the cost, power dissipation and bulk. One main part of the mixed signal system is the Analog-to-Digtal Converter (ADC), acting as interface of analog and digital circuit, ADC is very important to the whole system design.In this thesis we research the pipeline ADC which is very popular nowadays. Firstly, we analysis and introduce the characteristics of ADC, then compare some architectures of diffierent ADC types. Based on above analysis, we take the ADC system into sub-modules and do further research. These sub-modules are: sample and hold circuit, operational amplifier and comparator.Under the guidance of the theory mationed above, the whole circuit design is based on the process of Smic 0.13um Mixed-Signal with 3.3V power. At first, behavior level simulation of the circuit is done by Simulink, this can ensure the architecture and algorithm of the system is right, after that is circuit design, we emphasize in the operational amplifier and comparator design. The design goal is to achieve a 10 bit high speed low power ADC with 1.5 bit per stage structure. Because the offset of the comparator is not take an important part in this architecture, we choose the low static power dissipation comparator, i.e. dynamic comparator. The fully diffrential operational amplifier used in this thesis is simulated with Hspice, the results show that the dc gain of the operational amplifier is 86dB, the gain-bandwidth is 14.5MHz, 62 degree phase margin and power dissipation is 6.7mW.