Research On Key Design Techniques For 12-bit 250MSPS Pipelined ADC

In modern integrated circuits,analog-to-digital converters(ADCs) are a fundamental block serving to convert real-world analog signals into a format that digital signal technique will process. As CMOS processes continue to scale, the increased device cut-off frequency and the smaller parasitic capacitance allow more power-efficient and faster logic which improves the performance of the digital electronics, allowing more sophisticated and larger systems on a single chip. However, with lower intrinsic transistor output resistance, lower supply voltages, increased leakage currents, and higher device variability, the design of analog integrated circuits is facing a tremendous challenge. In short, the intrinsic gain of a single transistor stage decreases with finer CMOS processes. Thus, there is a new challenge before circuit engineer to design high-performance ADCs. Among various types of ADCs, pipelined ADC can make a better trade-off between accuracy, speed, chip area and power performance. So it is widely used in high speed wireless communication system.In this paper, analysis of and research on the structure of pipelined ADC is present first. Redundant calibration algorithm, the fundament of pipelined ADC makes it possible to realize a high-accuracy ADC with several simple quantizer. The MDAC circuit, made up of S/H, Sub-DAC, Adder and Amplifier, which is the key module of pipelined ADC, should be designed carefully about its quantification digits associated with properties such as gain, bandwidth and so on. SHA-less structure is selected in this paper for power efficient, meaning that the calibration for clock skew should be taken into consideration as well.In this paper,the computing method during the circuit design, the realizing of the circuit function, especially the design of the MDAC and amplifier are completely provided in Chapter 3, simultaneously with the technology of increasing the properties. The simulation results of the circuit are present in Chapter 4, which proves the desirable result.The proposed 12 bit 250MS/s Pipelined ADC was implemented in TSMC 65 nm CMOS process, with a 2.5V voltage supply and an input swing of-1V to +1V. The dynamic performance of the proposed ADC is tested under a 10.7MHz sine-wave input, the output of the first stage achieves a 14.87 bit resolution, which indicates a 91.3 d B Signal-to-Noise and Distortion Ratio(SNDR), and a 98.6 dB Spurious Free Dynamic Range(SFDR) is measured. The whole ADC circuits achieve an 11.96 bit ENOB, while the SFDR and SNDR are 86.7 dB and 73.7 dB respectively. When the input frequency increases to 108 MHz, the ENOB of the output of the first stage and the whole ADC still remain 13.89 bit and 11.81 bit respectively. A 90.3 dB SFDR and an 85.38 dB SNDR is measured at the output of the first stage, and an 81.9 dB SFDR and a 72.86 dB SNDR was measured at the output of the Pipelined ADC. The proposed pipelined ADC perfectly meets the design goals, and achieves good IF sampling performance at the same time.