The Key Technology Design For 16Bit 125MS/s Low-power ADC

ADCS are the key components in communication systems.With the development of process,mobile wireless communication systems' requirements for the ADC are more stringent,requiring it have both high performance and low-power characteristics.Especially in many IF-sampling communication system,require the ADC to sample input signals up to 300 MHz.In order to reduce receiver complexity and lower overall system cost,Pipeline ADC because of its performance is the most compromise,has become the preferred structure of wireless communication systems.Furthermore,CMOS is the preferred technology,due to its lower cost and suitability for implementing switched capacitor circuits.Pipeline ADCs with switching capacitor structure which are using this process to achieve,are widely used in today's mobile wireless communication systems.This thesis studied the circuits which fit the 16-bit 125MS/s pipeline ADC system based on the SMIC 0.18?m CMOS process.This thesis firstly introduces the performance parameters related to the ADC system and various common ADC structures.Then focus state on MDAC's overall structure and working principle which is the system's core module.The various non-ideal effects in the MDAC circuit,such as the charge injection effect and the non-linearity of the on-resistance,are introduced,and the corresponding elimination measures are given,such as bottom plate sampling technology,gate pressure bootstrap technology.According to the analysis of noise,power consumption and other factors combined with the actual situation,selected the overall architecture of the system to achieve,that is with SHA-less architecture,with five cascade way to achieve the overall accuracy,single-level quantitative bit is 4.Take the first level structure as an example,the detailed MDAC implementation circuit,such as residual amplifier,comparator circuit,and a gate voltage bootstrap circuit are given.The design of the MDAC core module residual amplifier is described,and several techniques used to improve performance,such as gain-boost technology,are made a brief description of their principle;The comparator has made some improvement and innovation,in order to reduce power consumption with realization of the premise of the function,Based on the SMIC 0.18?m CMOS process,the simulation results of each module circuit are given.And the whole ADC simulation under different process.The simulation results in the TT corner are shown as follow: amplifier with 479 MHz closed loop bandwidth,120 d B gain and 74.5° phase margin.;Comparator in the slowest case when differential input is the smallest,the working time is about 320ps;A bootstrapped switches with 97.8d B of SNR,110.3d B of SFDR;At 125 MHz sampling frequency,10.498046875 MHz input frequency,the ADC system achieved 95.1d B of SNDR,108.6d B of SFDR when 512 sampling points are adopted;The simulation results are close to the TT state in the corner of the FF process;In the SS corner,the process deviation is the most serious,achieved SNDR of 87.1d B and SFDR of 95.3d B.All the results show that this ADC design conforms to the initial setting of the system.