Research Of Pipelined SAR A/D Converter

As the CMOS technologies advance, more and more digital circuits are replaced by analog circuits, resulting from the rapid development of the digital signal processing technology. Analogy-to-digital converters(ADCs) are the bridge between anology signals and digital signals, which determine the performance of the whole system. In the field of the portable electronic applications, which require higher-performance ADCs, the study of the innovative ADC structures become meaningful, as the conventional structures could not meet the system requirement completely. Due to the perfect trade-off among speed, power, area and linearity, pipelined SAR analog-to-digital converters(pipelined SAR ADCs) have been widely researched, which is composed of pipeline ADC and SAR ADC. Multiplying digital-to-analog converter(MDAC) circuit is the core function module of the pipelined SAR ADC, which determines the performance of the pipelined SAR ADC, and its research has great significance.In this thesis, the overall structure and principle of the pipelined SAR ADC are introduced firstly with a focus on the study of the MDAC. A zero-crossing-based switch capacitor MDAC is proposed to meet the requirement of the pipelined SAR ADC by analyzing the traditional switch capacitor MDAC based on operational amplifier. The proposed MDAC completes the charge transfer by zero-crossing detector and current source instead of operational amplifier, which reduces both power and design complexity, compared to the traditional MDAC. Then, this thesis discusses the non-ideal factors of the zero-crossing-based pipelined SAR ADC, and puts forward some solutions. Next, the structure of the zero-crossing-based pipelined SAR ADC is optimized in terms of linearity, power and speed by matlab. Finally,a 10-bit 50MS/s zero-crossing-based pipelined SAR ADC is presented in SMIC 0.18μm CMOS technology. The proposed ADC is a two-stage pipeline ADC with a “5+6” structure, which achieves 10 b resolution by redundancy digital error correction method, and several key techniques are presented to improve the performance. “Half-gain” technique halves the gain of the first stage MDAC and the quantization rang of the second stage to reduce the power and design difficulty. Unidirectional dual phase charge transfertechnique reduces the overshoot and non-linear error from the zero-crossing detector and current source by using the coarse/fine currents and the level-shifting capacitor, which promises the speed of the charge transfer and reduces the current at the end of the charge transfer. Dummy cascode current sources improve the linearity and differetial mach without extra consumption. SAR dynamic control logic circuits offer a better performance in speed, area and power consumption by using dynamic logic unit instead of shifting register and flip-flop. The two-stage fully dynamic comparator is used to improve the comparator speed without static power consumption.The results of the circuit simulation show that the pipelined SAR ADC achieves 74.2d B SFDR, 61.3d B SNDR and 9.89 bit ENOB from 1.8V power supply at 50MS/s,with a power dissipation of 3.6m W.