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Efficient Implementation Of Useful Skew Optimization For Clock Tree

Posted on:2013-08-06Degree:MasterType:Thesis
Country:ChinaCandidate:X Z H XiFull Text:PDF
GTID:2268330392473844Subject:Software engineering
Abstract/Summary:PDF Full Text Request
With the development of semiconductor process, Market for the chip performancerequirements is getting higher and higher. For some paths which have great data delay,traditional optimization for date path can not meet the requirement of timing. difficult.In orderto further improve design performance,useful skew has become an necessary method for timingoptimization in physical design.Although Mainstreaming EDA(Electronic Design Automation)tools have ability to realizeuseful skew optimization, tools have obvious defects in optimization ability and require humanintervention to further improving design performance.This paper use encounter10.11as major experiment tool, through modify the test model’sclock tree synthesis file by script and adjust it’s clock path delay by ECO(Engineering ChangeOrder) to realize further useful skew. The main research contents are stated as follows:1.For EDA tool’s weakness in useful skew optimization to develop refine strategy. Thisstrategy use modifying clock tree synthesis file to realize utilizing slack from preceding logicstage and use ECO to further utilize slack from next logic stage. This strategy combines theoptimization ability of EDA tools and human intervention, increasing the effort of optimizationand decreasing the complexity of script realization.2.Using the classic Dijkstra algorithm to calculate the minimum timing ma rgin betweendifferent paths, and to simplify the original algorithm. Finally, it is applied in utilizing slack frompreceding logic stage successfully.3.Through to derivate the formula of connected wire delay, found the linear region betweenthe number of inserted buffer and wire delay, obvious simplified the progress of translating thewire delay to the number of inserted buffer. And based on this algorithm, proposed a new ECOstrategy which considers controlling unit density and reducing the number of inserted buffer.4.All research findings in this paper, have been program a set of script. They can be usedby other engineer easily to optimize other design, and then improving the project values of theoutcome.
Keywords/Search Tags:Clock Skew, Useful Skew, Interconnect Delay, Dijkstra Algorithm
PDF Full Text Request
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