Low Power Design Implementation For A Baseband Processor

With the development of mobile internet and hand device widely used,power consumption of integrated circuits become more and more important as well as frequency and area.And low power consumption technology would become a subject worthy of study in the design of integrated circuits.This paper analyzes the main components of CMOS circuit power consumption, its composition is mainly divided into static power and dynamic power consumption.And according to the different stages of chip design,including system design, circuit design, circuitdesign and realization process of the comprehensive,the paper studies the low power design methods commonly used in different stage.Low power design of digital circuits is throughout the whole stage in chip design. At present, the low power design methods are commonly used for clock gating, multi threshold voltage, power off and so on.This paper base on the BB baseband chip,at SMIC 130 nmG process, for the study,mainly to achieve the low power design in circuit synthesis and layout design stage. And based on this chip, according to different design stage, in the circuit synthesis stage studies the node capacitance optimization, multi threshold voltage technology, operand isolation technology, clock gating technology to decrease dynamic power and static power.At the same time focuses on using the UPF/CPF power constraints on the baseband processing chip BB for power shut off design and the clock tree synthesis of low power design in the layout design stage. After many experiments, the junction capacitance technology for power optimization can reach 2 percent, and the threshold voltage for power optimization design can reach 28%, operand isolation techniques in a combination circuit power optimization can reach 15 % clock gating optimization in sequential circuits can reach 70%, a low-power clock tree power technology for optimized clock tree can reach 50%.