Low Power Physical Design Research And Implementation Of YHFT-DX Chip

The last several decades has withness the rapidly development of integrated circuits.Espeically nowdays, as the CMOS technology scales into nanometer regions, theintegration and dominating frequency of a chip achieve a dramatically improvement.Nevertheless, the power-efficiency in MOS large-scale integration (LSIs) becomesextremely prominent, which is a burning issue in modern chip designs.In this dissertation, we focused on the realization of a low-power chip termed asYHFT-DX at physical-design level under65nm process, based on an analysis of low-power circuit structures in combination with some commonly low-power schemesincluding clock-gating buffer insertion, clock network optimation and multi-thresholdelement replacement. An overview of this dissertation is as follows.Firstly, a number reduction in clock-gating elements to diminish dynamic power isrealizated through a reasonable constraint between maximum fanout and minimumbit-width. Then, an optimizated clock tree is achieved in clock tree systhesis bycontrolling the number of the buffer, fanout and path levels, resulting in power-savingin terms of clock network. Finally, a HAM technique with respect to optimize leakagepower and area is proposed to improve the leakage power consumption of the chip,which also solves the problem of area overhead in conventional multi-threholdtechniuques.The experimental results show that the dynamic power dissipation of the chip isreduced by27.4%and the number of clock-gating elements is decreased by63byconstraining the fanout and width, while the power reduction achieves25.2%when onlyemploying clock-gating technique. Besides, the utilization of high-threshold elementsattains up to71.77%due to the HAM technique, resulting in19.49%reduction inleakage power.