Physical Design And Implementation Of Multi-point Clock Tree Synthesis In VLSI Design

In VLSI chip design, physical design is one of the steps in the the chip standarddesign cycle. The physical design task is to convert the front-end design netlist to thereal circuit which can be actually produced. It is time-consuming and laborious and isthe most complex step in the VLSI design. The premise of the produced chip canwork is to meet the timing requirements, thus the clock is the heart of the chip, theclock tree design occupies an extremely important position in the chip design. Asprocess technology continually improve, especially enter below65nm and40nm, theresulting uncertainty of the chip clock interference is increasing, hence high quality ofclock tree is related to the performance of the entire chip. Regular clock tree synthesishas been difficult to meet today’s large-scale chip design’s clock skew and powerconsumption requirements when done after clock tree synthesis. Because of theanti-interference ability and lower clock skew, H-type and X-type, X-H type andmesh-type clock network has been successfully applied to various types of chipdesign.In this paper, the main research is based on the multi-point clock trree synthesisphysical design and implementation with the top-level clock tree using clock spineplus clock mesh. The multi-point clock tree synthesis is a novel hybrid design, whichcombines a regular clock tree and pure clock mesh design’s many beneficial aspects.The implementation principle of multi-point clock tree synthesis is that clock signalstart from the clock source of the chip, propagate through clock spine which conbinesof custom large buffers internal rows, at last reach the top-level clock mesh networkdriven by clock spine in top-level redistribution layer, and then transmitted to clockroot buffers which distribute in the inside of sub-modules and whose input pinmounted to the the top layer clock mesh, and then in the interior of each module，eachoutput pin of root buffer is as one clock source to do clock tree synthesis. When thecircuit introduced OCV (on-chip variation) to calculate the timing, compared withregular clock tree and a pure clock mesh, multi-point clock tree has a lower clockskew, lower clock delay and less timing violation.the platform for implementing multi-point clock tree synthesis is the Linuxoperating system, using the back-end EDA tools Cadence’s Encounter and Synopsys’sIC Compiler.