Design Of High Speed Pipeline ADC Based On Ethernet Chip

Gigabit Ethernet chips can meet the needs of terminals for wide bandwidth.The development of Gigabit Ethernet chips is the only way to break foreign technical barriers and realize the development of the Internet of Things and cloud computing.As the key technical module of the Ethernet chip,the analog-to-digital converter(ADC)is a bridge connecting analog and digital circuits.With the development of integrated circuits,requirements for pipeline ADC conversion speed are getting higher and higher.With the continuous shrinking of semiconductor process size and the reduction of transistor output impedance,designing high-gain op amps has become a technical difficulty for Pipeline ADC design.At the same time,Pipeline ADC requires multi-level MDAC circuits,which consume a lot of power consumption and occupy a lot of chip area.First,this paper adopts a fully customized technical route and fully considers the high-speed and high-precision requirements of the Ethernet chip for the analog-to-digital converter,and decides to adopt an 8-level,1.5-bit-per-level Pipeline ADC structure.The analog signal of the analog-to-digital converter in this paper directly enters the sample-and-hold circuit(SH)and the sub-analog-to-digital converter(Sub ADC)circuit;the digital output of the Sub ADC simultaneously controls the operation of the multiplying digital-to-analog converter(MDAC)and the comparison level of the next stage Sub ADC size.The optimization of this kind of Pipeline ADC algorithm,compared with the traditional 8-level 1.5bit-per-level Pipeline ADC structure,uses less one-level MDAC circuit,which saves about 3m A of power consumption,and at the same time increases the conversion rate of the Pipeline ADC.Finally,the optimized Pipeline ADC algorithm is used to achieve a pipeline ADC design with a sampling rate of 125MHz and a resolution of 9bit under a supply voltage of 2.5V.Second,before the design of the Pipeline ADC circuit,in order to ensure the correctness of the Pipeline ADC theoretical calculation and the correctness of the Pipeline ADC algorithm,Matlab was used to model and simulate the Pipeline ADC in Simulink,which successfully verified the rationality of the Pipeline ADC algorithm and successfully simulated it.The impact of non-ideal characteristics on the output of Pipeline ADC is described.Third,this circuit design uses Cadence's EDA tool,uses standard SMIC 65nm process,and uses Spectre simulation tool to design and simulate the circuit modules that constitute the Pipeline ADC this time.The main in-depth research is on the following circuit sub-modules of Pipeline ADC:(1)Sample-and-hold circuit:samples the analog input signal and stably transmits it to the next-level circuit.(2)The operational amplifier is the most critical component of the sample-and-hold circuit and the MDAC circuit.This paper uses a two-stage operational amplifier structure,the first stage is a sleeve-type cascode structure.The second stage uses a five-tube differential op amp structure.Under typical simulation conditions,the gain of the op amp is 83.7d B and the bandwidth(GBW)is 1.75GHz,which meets the requirements of the Pipeline ADC for the gain and bandwidth of the op amp.(3)MDAC circuit:realize the functions of signal sampling,digital-to-analog conversion,subtraction and residual amplification.(4)Comparator circuit:The minimum bandwidth of simulation under the full process angle is 1.7GHz,which meets the requirements of Pipeline ADC conversion speed.(5)Two-phase non-overlapping clock circuit,through the two-phase non-overlapping clock control Pipeline ADC stage and stage alternate work.(6)Delay adding unit and digital correction circuit:The delay adding unit synchronizes the results of each level of analog-to-digital conversion,and outputs the synchronized results to the digital correction circuit for misalignment addition to obtain the final digital output.The delay adding unit adopts a new timing alignment algorithm.Compared with traditional algorithms,fewer D flip-flops are used to complete timing alignment,reducing chip area and power consumption.(7)The charge pump LDO circuit uses charge pump technology,LDO technology and RC filter technology to obtain stable reference voltages V_REFP and V_REFNand common mode voltage V_OM.Fourth,after completing the design and verification simulation of the sub-module circuit,use the Cadence tool to conduct layout design and overall performance simulation of Pipeline ADC.Without adding non-ideal factors,input signal frequency is 24MHz,the Pre-simulation results is:SNDR=55.7d B,ENOB=8.96bit,SFDR=66.19d B,SNR=56.41d B,THD=-63.9d B,INL=0.77LSB,DNL=0.28LSB,the power consumption is 23.8m A.Pipeline ADC has a very strong anti-interference ability.When the frequency is 1MHz,the amplitude is 20m V power supply disturbance,the charge pump LDO adds 13.78?resistance mismatch,the comparator adds 9m V mismatch,and the post-simulation is performed under the typical process angle,The ENOB of Pipeline ADC still has 8.06 bit.