Study On The Low Power Dissipation For Analog-to-Digital Converter

The design methodology for system-on-chip has been shifted from digital orientation to mixed-signal type. It is necessary to integrated mixed-signal module and base-band processor in a single chip especially in the field of wireless voice and digital communication. Chips of this type usually include parts of digital and analog base-band, power management, radio frequency (RF) and phase loop lock (PLL). Analog-to-digital converter (ADC) is one of the most important building blocks in portable devices where low power dissipation is an essential factor.With the development of integrated circuit technology, typical dies size has reached deep sub-micrometer, and typical voltage has already lower than 1V. The balance between power dissipation and circuit performance is a serious problem with the effect of noise and short channel effect.Pipeline ADC could achieve high speed and medium-to-high resolution, for it is serial in cascade stage and parallel as a whole. The special architecture paves the way for power optimization in system and in each module by various measures. The power optimization arithmetic including resolution distribution, capacitor scaling, current control of each stage and architecture selection of SHA and comparator is proposed to instruct the design of pipeline ADC. An 8-bit 200-MS/s pipeline converter occupying 0.567mm~2 is presented in 0.18μm CMOS from 1.8-V supply by the improved power optimization approach in which improved sample and hold amplifier and comparator are adopted to compensate the mismatch from capacitor and offset from capacitor. Test result indicates that it consumes 172mW at 200MS/s with 45.5dB SNDR, 57.5dB SFDR under 100MHz input signal, while DNL and INL are within +0.69/-0.6 and +0.75/-1.05LSB respectively.