Study On ADC For CMOS Image Sensor

This project is part of research work on a paramount project to tackle in Tianjin Science & Technology Committee "High Performance High Dynamic CMOS Image Sensor Design". What I should do is to design the interface circuit block of the sensor. It is called Analog-to-Digital Converter. It can convert the analog signal, which has been sampled and amplified by the sensor to digital signals. And then the image is presented by strong digital processing ability of computer or DSP. Based on the Top-Down full custom design method, after analyzing the need of the sensor and the comparison between several kinds of ADC, the Pipeline architecture has been selected eventually. In a pipelined analog to digital converter, a higher throughput rate can be obtained because a new sample can be taken as soon as the first stage of the pipeline has finished processing the old sample. Each block of the pipeline ADC has been designed in detail based on the existing framework (including the architecture designing, function simulating and layout with validation). Popular CMOS process (0.35um P-sub N-well 2p4m CMOS technology which is offered by Chartered CO.,LTD.) has been used in design flow and this makes ADC more conv-enient to be compatible with the whole sensor system and to realize the SOC. The EDA tools used in the project are HSPICE and Composer Spectre, Virtuoso, Dracula, Diva, from Cadence CO., LTD. The pipeline ADC presented in the thesis totally has 4 stages. 4bits, 3bits, 3bits, 3bits have been converted by each stage. The converter which has a good tradeoff between conversion speed and conversion precision and 20Msample/s sample rate has been obtained by designing the high performance op amplifier with 90dB gain and about 700M bandwidth. We realize the op amp as a 3 stages, full-differential switch-capacitor architecture. The design method, circ-uit architecture and simulation result have been proposed completely. Besides, several supplementary blocks are also presented in this thesis. What I have done is as follows: Analysis and design on system, simulation and layout of clock block, bias block and MDAC block, present the test bench for testing work.